| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix tests/simple/specify.v | Clifford Wolf | 2018-03-27 | 1 | -2/+2 |
| * | First draft of Verilog parser support for specify blocks and parameters. | Udi Finkelstein | 2018-03-27 | 1 | -0/+31 |
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index : iCE40/yosys | |
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