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| author | Udi Finkelstein <github@udifink.com> | 2018-03-04 23:35:08 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-03-27 14:34:00 +0200 |
| commit | 6378e2cd46711fed551ecf3201cee1f174d7053d (patch) | |
| tree | 2560746b61bd2da76e8add38ca57adc30d086a09 /tests/simple/specify.v | |
| parent | f3eaa0ffa54ddaea4bf4e04acc1b2e019e22484a (diff) | |
| download | yosys-6378e2cd46711fed551ecf3201cee1f174d7053d.tar.gz yosys-6378e2cd46711fed551ecf3201cee1f174d7053d.tar.bz2 yosys-6378e2cd46711fed551ecf3201cee1f174d7053d.zip | |
First draft of Verilog parser support for specify blocks and parameters.
The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
Diffstat (limited to 'tests/simple/specify.v')
| -rw-r--r-- | tests/simple/specify.v | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/tests/simple/specify.v b/tests/simple/specify.v new file mode 100644 index 000000000..74563509e --- /dev/null +++ b/tests/simple/specify.v @@ -0,0 +1,31 @@ +module test_specify; + +specparam a=1; + +specify +endspecify + +specify +(A => B) = ( 1 ) ; +(A- => B) = ( 1,2 ) ; +(A+ => B) = ( 1,2,3 ) ; +(A => B) = ( + 1.1, 2, 3, + 4, 5.5, 6.6 +) ; +(A => B) = ( + 1.1, 2, 3, + 4, 5.5, 6.6 , + 7.7, 8.8, 9, + 10.1, 11, 12 +) ; +specparam a=1; +specparam [1:2] asasa=1; +endspecify + +specify +specparam a=1:2:3; +endspecify + +endmodule + |