iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Revert "Add test that is expecting to fail"	Eddie Hung	2019-10-08	1	-20/+0
*	Add test that is expecting to fail	Eddie Hung	2019-10-02	1	-0/+20
*	Revert to using clean	Eddie Hung	2019-08-27	1	-1/+1
*	Wire with init on FF part, 1'bx on non-FF part	Eddie Hung	2019-08-24	1	-1/+3
*	Blocking assignment	Eddie Hung	2019-08-23	1	-1/+1
*	In sat: 'x' in init attr should not override constant	Eddie Hung	2019-08-22	2	-1/+5
*	support repeat loops with constant repeat counts outside of constant functions	Zachary Snow	2019-04-09	2	-0/+48
*	Allow $size and $bits in verilog mode, actually check test case	Clifford Wolf	2017-09-29	2	-0/+34
*	Added yet another resource sharing test case	Clifford Wolf	2014-07-20	2	-0/+49
*	now ignore init attributes on non-register wires in sat command	Clifford Wolf	2014-07-05	2	-0/+19
*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12	2	-2/+2
*	Added test cases for expose -evert-dff	Clifford Wolf	2014-02-08	2	-0/+48
*	Added splice command	Clifford Wolf	2014-02-07	2	-0/+28
*	Added counters sat test case	Clifford Wolf	2014-02-06	2	-0/+45
*	Added test cases for sat command	Clifford Wolf	2014-02-04	6	-0/+126