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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:42:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:43:08 -0700 |
| commit | 51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d (patch) | |
| tree | 2a70d1550ab81a96f4c383524fd4c66bdef2c7b0 /tests/sat | |
| parent | c50d68653d093a8daa47f589836e6178be82b54f (diff) | |
| download | yosys-51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d.tar.gz yosys-51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d.tar.bz2 yosys-51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d.zip | |
In sat: 'x' in init attr should not override constant
Diffstat (limited to 'tests/sat')
| -rw-r--r-- | tests/sat/initval.v | 4 | ||||
| -rw-r--r-- | tests/sat/initval.ys | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/tests/sat/initval.v b/tests/sat/initval.v index 5b661f8d6..d46ccae48 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,6 +1,7 @@ module test(input clk, input [3:0] bar, output [3:0] foo); reg [3:0] foo = 0; reg [3:0] last_bar = 0; + reg [3:0] asdf = 4'b1xxx; always @* foo[1:0] <= bar[1:0]; @@ -11,5 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; + always @* + asdf[2:0] <= 3'b111; + assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 2079d2f34..3d88aa971 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc;; +proc; sat -seq 10 -prove-asserts |