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* Merge pull request #1638 from YosysHQ/eddie/fix1631Eddie Hung2020-02-051-0/+66
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| * More rigorous testEddie Hung2020-01-161-7/+34
| * clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*Eddie Hung2020-01-151-0/+39
* | Even more obvious testcaseEddie Hung2019-12-111-6/+5
* | Make testcase clearer with \o having its own initEddie Hung2019-12-111-0/+2
* | Add test: 'Warning: ignoring initial value on non-register: \o'Eddie Hung2019-12-111-0/+10
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* Revert "Add test that is expecting to fail"Eddie Hung2019-10-081-20/+0
* Add test that is expecting to failEddie Hung2019-10-021-0/+20
* Revert to using cleanEddie Hung2019-08-271-1/+1
* Wire with init on FF part, 1'bx on non-FF partEddie Hung2019-08-241-1/+3
* Blocking assignmentEddie Hung2019-08-231-1/+1
* In sat: 'x' in init attr should not override constantEddie Hung2019-08-222-1/+5
* support repeat loops with constant repeat counts outside of constant functionsZachary Snow2019-04-092-0/+48
* Allow $size and $bits in verilog mode, actually check test caseClifford Wolf2017-09-292-0/+34
* Added yet another resource sharing test caseClifford Wolf2014-07-202-0/+49
* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-052-0/+19
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-122-2/+2
* Added test cases for expose -evert-dffClifford Wolf2014-02-082-0/+48
* Added splice commandClifford Wolf2014-02-072-0/+28
* Added counters sat test caseClifford Wolf2014-02-062-0/+45
* Added test cases for sat commandClifford Wolf2014-02-046-0/+126