iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Moved all tests in arch sub directory	Miodrag Milanovic	2019-10-18	20	-429/+0
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*	hierarchy - proc reorder	Miodrag Milanovic	2019-10-18	4	-9/+10
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*	Cleanup and formating	Miodrag Milanovic	2019-10-04	4	-2/+4
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*	split latches into separate checks	Miodrag Milanovic	2019-10-04	2	-41/+24
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*	check muxes per type	Miodrag Milanovic	2019-10-04	2	-42/+37
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*	check ff's separately	Miodrag Milanovic	2019-10-04	2	-26/+14
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*	Cleanup top modules and not used defines	Miodrag Milanovic	2019-10-04	5	-44/+5
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*	remove alu test	Miodrag Milanovic	2019-10-04	2	-36/+0
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*	run-test.sh Move $x at end of line.	Sergey	2019-10-01	1	-1/+1
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*	Add new tests for Anlogic architecture	SergeyDegtyar	2019-09-23	22	-0/+535
	Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present.