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* tests: aiger test for wire->start_offset != 0Eddie Hung2020-05-022-0/+41
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* tests/aiger: Add missing .gitignoreMarcin Koƛcielnicki2020-02-151-0/+2
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* Add testcasesEddie Hung2020-01-072-0/+17
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* tests/aiger: write Yosys outputEddie Hung2020-01-071-2/+2
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* tests: use optional ABCEXTERNAL when specifiedGabriel L. Somlo2019-06-271-2/+12
| | | | | | | | | Commits 65924fd1, abc40924, and ebe29b66 hard-code the invocation of yosys-abc, which fails if ABCEXTERNAL was specified during the build. Allow tests to utilize an optional, externally specified abc binary. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
* Update some .gitignore filesClifford Wolf2019-06-201-2/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make tests/aiger less chattyClifford Wolf2019-06-191-4/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add some more commentsEddie Hung2019-06-101-1/+6
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* Test *.aag too, by using *.aig as referenceEddie Hung2019-06-071-0/+19
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* Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
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* Add symbols to AIGER test inputs for ABCEddie Hung2019-06-0722-8/+40
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* Add tests/aiger/.gitignoreClifford Wolf2019-04-191-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Support and differentiate between ASCII and binary AIG testingEddie Hung2019-02-081-1/+5
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* Add binary AIGs converted from AAGEddie Hung2019-02-0814-0/+51
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* Rename ASCII testsEddie Hung2019-02-0615-0/+96