Commit message (Collapse) | Author | Age | Files | Lines | |
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* | tests: aiger test for wire->start_offset != 0 | Eddie Hung | 2020-05-02 | 2 | -0/+41 |
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* | tests/aiger: Add missing .gitignore | Marcin KoĆcielnicki | 2020-02-15 | 1 | -0/+2 |
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* | Add testcases | Eddie Hung | 2020-01-07 | 2 | -0/+17 |
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* | tests/aiger: write Yosys output | Eddie Hung | 2020-01-07 | 1 | -2/+2 |
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* | tests: use optional ABCEXTERNAL when specified | Gabriel L. Somlo | 2019-06-27 | 1 | -2/+12 |
| | | | | | | | | | Commits 65924fd1, abc40924, and ebe29b66 hard-code the invocation of yosys-abc, which fails if ABCEXTERNAL was specified during the build. Allow tests to utilize an optional, externally specified abc binary. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com> | ||||
* | Update some .gitignore files | Clifford Wolf | 2019-06-20 | 1 | -2/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Make tests/aiger less chatty | Clifford Wolf | 2019-06-19 | 1 | -4/+6 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add some more comments | Eddie Hung | 2019-06-10 | 1 | -1/+6 |
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* | Test *.aag too, by using *.aig as reference | Eddie Hung | 2019-06-07 | 1 | -0/+19 |
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* | Use ABC to convert AIGER to Verilog, then sat against Yosys | Eddie Hung | 2019-06-07 | 1 | -21/+15 |
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* | Add symbols to AIGER test inputs for ABC | Eddie Hung | 2019-06-07 | 22 | -8/+40 |
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* | Add tests/aiger/.gitignore | Clifford Wolf | 2019-04-19 | 1 | -0/+2 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Support and differentiate between ASCII and binary AIG testing | Eddie Hung | 2019-02-08 | 1 | -1/+5 |
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* | Add binary AIGs converted from AAG | Eddie Hung | 2019-02-08 | 14 | -0/+51 |
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* | Rename ASCII tests | Eddie Hung | 2019-02-06 | 15 | -0/+96 |