iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	tests: aiger test for wire->start_offset != 0	Eddie Hung	2020-05-02	2	-0/+41
*	tests/aiger: Add missing .gitignore	Marcin Kościelnicki	2020-02-15	1	-0/+2
*	Add testcases	Eddie Hung	2020-01-07	2	-0/+17
*	tests/aiger: write Yosys output	Eddie Hung	2020-01-07	1	-2/+2
*	tests: use optional ABCEXTERNAL when specified	Gabriel L. Somlo	2019-06-27	1	-2/+12
*	Update some .gitignore files	Clifford Wolf	2019-06-20	1	-2/+1
*	Make tests/aiger less chatty	Clifford Wolf	2019-06-19	1	-4/+6
*	Add some more comments	Eddie Hung	2019-06-10	1	-1/+6
*	Test .aag too, by using .aig as reference	Eddie Hung	2019-06-07	1	-0/+19
*	Use ABC to convert AIGER to Verilog, then sat against Yosys	Eddie Hung	2019-06-07	1	-21/+15
*	Add symbols to AIGER test inputs for ABC	Eddie Hung	2019-06-07	22	-8/+40
*	Add tests/aiger/.gitignore	Clifford Wolf	2019-04-19	1	-0/+2
*	Support and differentiate between ASCII and binary AIG testing	Eddie Hung	2019-02-08	1	-1/+5
*	Add binary AIGs converted from AAG	Eddie Hung	2019-02-08	14	-0/+51
*	Rename ASCII tests	Eddie Hung	2019-02-06	15	-0/+96