| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v | Clifford Wolf | 2013-04-07 | 1 | -4/+4 | |
| * | Added EXTRA_TARGETS Makefile variable | Clifford Wolf | 2013-03-28 | 1 | -1/+1 | |
| * | Tiny bugfix in simlib.v | Clifford Wolf | 2013-03-26 | 1 | -1/+0 | |
| * | Fixed stdcells.v for $adff with undef reset value | Clifford Wolf | 2013-03-24 | 1 | -63/+68 | |
| * | More support code for $sr cells | Clifford Wolf | 2013-03-14 | 1 | -0/+21 | |
| * | added .gitignore files | Clifford Wolf | 2013-01-05 | 1 | -0/+1 | |
| * | initial import | Clifford Wolf | 2013-01-05 | 5 | -0/+2447 | |
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index : iCE40/yosys | |
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