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* synth_intel_alm: VQM supportDan Ravensloft2020-04-152-6/+3
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* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1518-1/+1453
| | | | | | | | By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-105-2/+137
|\ | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-1/+3
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| * ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-1/+3
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| * ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-062-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
| * ice40: match memory inference attribute values case insensitive.whitequark2020-02-061-0/+1
| | | | | | | | LSE/Synplify use case insensitive matching.
| * ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-061-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
* | Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-035-13/+121
|\ \ | | | | | | "techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
| * | cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmpEddie Hung2020-04-031-1/+1
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| * | cmp2lcu: fail if `LUT_WIDTH < 2Eddie Hung2020-04-031-1/+1
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| * | synth: only techmap cmp2{lut,lcu} if -lutEddie Hung2020-04-031-1/+1
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| * | synth: use +/cmp2lcu.v in generic 'synth' tooEddie Hung2020-04-031-2/+2
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| * | Cleanup +/cmp2lut.vEddie Hung2020-04-031-8/+0
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| * | synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'Eddie Hung2020-04-031-2/+1
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| * | +/cmp2lcu.v to work efficiently for fully/partially constant inputsEddie Hung2020-04-031-33/+42
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| * | Refactor +/cmp2lcu.v into recursive techmapEddie Hung2020-04-031-38/+65
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| * | CleanupEddie Hung2020-04-031-31/+28
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| * | Cleanup cmp2lcu.vEddie Hung2020-04-031-16/+16
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| * | techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcuEddie Hung2020-04-032-0/+84
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| * | cmp2lut: comment out unused since 362f4f9Eddie Hung2020-04-031-8/+8
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* | | Merge pull request #1767 from YosysHQ/eddie/idstringsEddie Hung2020-04-0216-387/+387
|\ \ \ | | | | | | | | IdString: use more ID::*, make them easier to use, speed up IdString::in()
| * | | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-0216-366/+366
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| * | | kernel: use more ID::*Eddie Hung2020-04-025-26/+26
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* / / simcells.v: Generate the fine FF cell types by a python script.Marcin Kościelnicki2020-04-022-19/+270
|/ / | | | | | | | | | | This makes adding more FF types in the future much more manageable. Fixes #1824.
* | Fix indentation in `techlibs/ice40/synth_ice40.cc`.Alberto Gonzalez2020-04-011-4/+4
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* | Merge pull request #1794 from YosysHQ/dave/mince-abc9-fixDavid Shah2020-03-211-0/+1
|\ \ | | | | | | ice40: Map unmapped 'mince' DFFs to gate level
| * | ice40: Map unmapped 'mince' DFFs to gate levelDavid Shah2020-03-201-0/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ice40: Fix typos in SPRAM ABC9 timing specsSylvain Munaut2020-03-201-2/+2
|/ / | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | xilinx: Mark IOBUFDS.IOB as external padMarcin Kościelnicki2020-03-202-1/+2
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* | ice40: Fix SPRAM model to keep data stable if chipselect is lowSylvain Munaut2020-03-141-5/+8
| | | | | | | | | | | | | | | | According to the official simulation model, and also cross-checked on real hardware, the data output of the SPRAM when chipselect is low is kept stable. It doesn't go undefined. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Fix invalid verilog syntaxMiodrag Milanovic2020-03-141-1/+1
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* | Merge pull request #1716 from zeldin/ecp5_fixN. Engelhardt2020-03-091-2/+0
|\ \ | | | | | | ecp5: remove unused parameter from \$__ECP5_PDPW16KD
| * | remove unused parametersN. Engelhardt2020-03-061-3/+0
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| * | ecp5: Add missing parameter to \$__ECP5_PDPW16KDMarcus Comstedt2020-02-221-0/+1
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* | | ice40: fix specify for ICE40_{LP,U}Eddie Hung2020-03-051-4/+4
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* | | ice40: fix implicit signal in specify, also clamp negative times to 0Eddie Hung2020-03-041-22/+22
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* | | Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1Eddie Hung2020-03-044-109/+244
|\ \ \ | | | | | | | | xilinx: cleanup DSP48E1 handling for abc9
| * | | xilinx: consider DSP48E1.ADREGEddie Hung2020-03-044-5/+8
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| * | | xilinx: cleanup DSP48E1 handling for abc9Eddie Hung2020-03-043-86/+125
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| * | | xilinx: improve specify for DSP48E1Eddie Hung2020-03-041-32/+116
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| * | | xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.vEddie Hung2020-03-042-5/+14
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* | | | Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-032-6/+39
|\ \ \ \ | |/ / / |/| | | Add -flowmap option to `synth{,_ice40}`
| * | | Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-282-6/+39
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* | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-0230-1440/+2803
|\ \ \ \ | | | | | | | | | | abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
| * | | | Remove RAMB{18,36}E1 from cells_xtra.pyEddie Hung2020-02-271-2/+2
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| * | | | xilinx: Update RAMB* specify entriesEddie Hung2020-02-271-11/+42
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| * | | | ice40: add delays to SB_CARRYEddie Hung2020-02-271-0/+30
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| * | | | xilinx: add delays to INVEddie Hung2020-02-271-0/+3
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| * | | | More +/ice40/cells_sim.v fixesEddie Hung2020-02-271-27/+27
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