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* Fix TRELLIS_FF simulation modelMiodrag Milanovic2019-08-311-6/+7
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* ecp5_gsr: Fix typoDavid Shah2019-08-311-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-3013-136/+180
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| * ecp5: Add simulation equivalence check for Diamond FF implementationsDavid Shah2019-08-303-0/+87
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives.whitequark2019-08-305-95/+60
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| * ecp5: allow (and enable by default) GSR on FD/IFS/OFS primitives.whitequark2019-08-301-35/+20
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| * ecp5: add missing FD primitives.whitequark2019-08-302-72/+76
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| * ecp5: fix CEMUX on IFS/OFS primitives.whitequark2019-08-302-18/+18
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| * Rename boxes tooEddie Hung2019-08-293-3/+3
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| * Do not overwrite LUT paramEddie Hung2019-08-281-1/+0
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| * Trailing commaEddie Hung2019-08-281-1/+1
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| * Adapt to $__ICE40_CARRY_WRAPPEREddie Hung2019-08-281-3/+5
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| * Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with"Eddie Hung2019-08-281-0/+45
| | | | | | | | This reverts commit 2aedee1f0e0f6a6214241f51f5c12d4b67c3ef6f.
| * Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason withEddie Hung2019-08-281-45/+0
| | | | | | | | CARRY_WRAPPER in the same way since I0 and I3 could be used
| * Update box size and timingsEddie Hung2019-08-283-12/+12
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| * Update to new $__ICE40_CARRY_WRAPPEREddie Hung2019-08-281-11/+8
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| * Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendorEddie Hung2019-08-281-3/+8
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* | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-2813-248/+835
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| * Merge pull request #1332 from YosysHQ/dave/ecp5gsrDavid Shah2019-08-286-54/+212
| |\ | | | | | | ecp5: Add GSR and SGSR support
| | * ecp5: Add GSR supportDavid Shah2019-08-276-54/+212
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | xilinx: Add SRLC16E primitive.Marcin Kościelnicki2019-08-271-1/+21
| | | | | | | | | | | | Fixes #1331.
| * | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-261-0/+8
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| * | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-1/+1
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| * \ \ Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-233-18/+36
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| * \ \ \ Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-2329-299/+1059
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| * | | | | move attributes to wiresMarcin Kościelnicki2019-08-136-283/+537
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| * | | | | minor review fixesMarcin Kościelnicki2019-08-131-1/+1
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| * | | | | review fixesMarcin Kościelnicki2019-08-131-18/+27
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| * | | | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-136-71/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
* | | | | | Merge branch 'master' into eddie/xilinx_srlEddie Hung2019-08-261-0/+8
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| * | | | | Add undocumented featureEddie Hung2019-08-231-0/+8
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* | | | | xilinx_srl now copes with word-level flops $dff{,e}Eddie Hung2019-08-231-8/+3
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* | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-233-15/+30
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| * | | | Forgot oneEddie Hung2019-08-231-1/+2
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| * | | Put abc_* attributes above portEddie Hung2019-08-233-14/+28
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* | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-2214-92/+961
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| * | Fix missing newline at end of fileClifford Wolf2019-08-221-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #1289 from mmicko/anlogic_fixesClifford Wolf2019-08-225-91/+162
| |\ \ | | | | | | | | Anlogic fixes and optimization
| | * \ Merge remote-tracking branch 'upstream/master' into anlogic_fixesMiodrag Milanovic2019-08-187-165/+37
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| | * | | Proper arith for Anlogic and use standard passMiodrag Milanovic2019-08-125-91/+162
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| * | | Fix missing newline at end of fileClifford Wolf2019-08-221-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge pull request #1281 from mmicko/efinixClifford Wolf2019-08-229-0/+798
| |\ \ \ | | | | | | | | | | Initial support for Efinix Trion series FPGAs
| | * | | Fix formatingMiodrag Milanovic2019-08-111-2/+2
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| | * | | one bit enable signalMiodrag Milanovic2019-08-111-1/+1
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| | * | | fix mixing signals on FF mappingMiodrag Milanovic2019-08-111-4/+4
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| | * | | Replaced custom step with setundefMiodrag Milanovic2019-08-113-91/+1
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| | * | | Fixed data widthMiodrag Milanovic2019-08-111-2/+2
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| | * | | Adding new pass to fix carry chainMiodrag Milanovic2019-08-113-0/+124
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| | * | | cleanupMiodrag Milanovic2019-08-111-4/+7
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| | * | | Fix COMiodrag Milanovic2019-08-091-26/+24
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