Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Add "synth_ice40 -json" | Clifford Wolf | 2018-06-13 | 1 | -9/+22 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix ice40_opt for cases where a port is connected to a signal with width != 1 | Clifford Wolf | 2018-06-11 | 1 | -9/+25 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Make -nordff the default in "prep" | Clifford Wolf | 2018-05-30 | 1 | -9/+13 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Avoid mixing module port declaration styles in ice40 cells_sim.v | Olof Kindgren | 2018-05-17 | 1 | -43/+23 |
| | | | | | | The current code requires workarounds for several simulators For modelsim, the file must be compiled with -mixedansiports and xsim needs --relax. | ||||
* | Merge pull request #537 from mithro/yosys-vpr | Clifford Wolf | 2018-05-04 | 4 | -11/+48 |
|\ | | | | | Improving Yosys when used with VPR | ||||
| * | Improving vpr output support. | Tim 'mithro' Ansell | 2018-04-18 | 4 | -7/+40 |
| | | | | | | | | | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`. | ||||
| * | synth_ice40: Rework the vpr blif output slightly. | Tim 'mithro' Ansell | 2018-04-18 | 1 | -4/+8 |
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* | | Add "synth_intel --noiopads" | Clifford Wolf | 2018-04-30 | 1 | -2/+11 |
|/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add "synth_ice40 -nodffe" | Clifford Wolf | 2018-04-16 | 1 | -2/+11 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal ↵ | c60k28 | 2018-03-31 | 11 | -178/+233 |
| | | | | value for the POWER_UP parameter. Fixed and tested Cyclone V device | ||||
* | coolrunner2: Add an ANDTERM/XOR between chained FFs | Robert Ou | 2018-03-31 | 1 | -0/+58 |
| | | | | | | | In some cases (e.g. the low bits of counters) the design might end up with a flip-flop whose input is directly driven by another flip-flop. This isn't possible in the Coolrunner-II architecture, so add a single AND term and XOR in this case. | ||||
* | coolrunner2: Split multi-bit nets | Robert Ou | 2018-03-31 | 1 | -0/+1 |
| | | | | | The PAR tool doesn't expect any "dangling" nets with no drivers nor sinks. By splitting the nets, clean removes them. | ||||
* | coolrunner2: Add extraction for TFFs | Robert Ou | 2018-03-31 | 3 | -0/+54 |
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* | Squelch trailing whitespace, including meta-whitespace | Larry Doolittle | 2018-03-11 | 4 | -16/+16 |
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* | Add Xilinx RAM64X1D and RAM128X1D simulation models | Clifford Wolf | 2018-03-07 | 4 | -23/+30 |
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* | Add "synth -noshare" | Clifford Wolf | 2018-03-04 | 1 | -2/+11 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -0/+24 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | coolrunner2: Move LOC attributes onto the IO cells | Robert Ou | 2018-01-17 | 1 | -0/+2 |
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* | Add "dffinit -highlow" and fix synth_intel | Clifford Wolf | 2018-01-09 | 1 | -1/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix minor typo in "prep" help message | Clifford Wolf | 2017-12-19 | 1 | -1/+1 |
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* | Fix port names in SB_IO_OD | Graham Edgecombe | 2017-12-10 | 1 | -18/+18 |
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* | Remove trailing comma from SB_IO_OD port list | Graham Edgecombe | 2017-12-10 | 1 | -1/+1 |
| | | | | This isn't compatible with Icarus Verilog. | ||||
* | Fix spelling in -vpr help for synth_ice40 | Tim Ansell | 2017-12-08 | 1 | -1/+1 |
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* | Merge pull request #462 from daveshah1/up5k | Clifford Wolf | 2017-11-28 | 1 | -0/+263 |
|\ | | | | | Add remaining UltraPlus cells to ice40 techlib | ||||
| * | Add remaining UltraPlus cells to ice40 techlib | David Shah | 2017-11-28 | 1 | -0/+263 |
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* | | Merge pull request #455 from daveshah1/up5k | Clifford Wolf | 2017-11-18 | 1 | -0/+103 |
|\| | | | | | Add UltraPlus specific cells to ice40 techlib | ||||
| * | Remove unnecessary keep attributes | David Shah | 2017-11-18 | 1 | -5/+5 |
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| * | Merge branch 'master' into up5k | David Shah | 2017-11-17 | 2 | -5/+29 |
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| * | | Add some UltraPlus cells to ice40 techlib | David Shah | 2017-11-16 | 1 | -0/+103 |
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* | | | Merge pull request #453 from dh73/master | Clifford Wolf | 2017-11-18 | 10 | -5/+312 |
|\ \ \ | |_|/ |/| | | Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells | ||||
| * | | Initial Cyclone 10 support | dh73 | 2017-11-08 | 5 | -1/+308 |
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| * | | Organizing Speedster file names | dh73 | 2017-11-08 | 5 | -4/+4 |
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* / | Add "synth_ice40 -vpr" | Clifford Wolf | 2017-11-16 | 2 | -5/+29 |
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* | Clean whitespace and permissions in techlibs/intel | Larry Doolittle | 2017-10-05 | 21 | -190/+190 |
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* | Rename "write_verilog -nobasenradix" to "write_verilog -decimal" | Clifford Wolf | 2017-10-03 | 1 | -4/+1 |
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* | Tested and working altsyncarm without init files | dh73 | 2017-10-01 | 2 | -57/+59 |
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* | Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵ | dh73 | 2017-10-01 | 30 | -727/+2954 |
| | | | | M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now | ||||
* | Add first draft of eASIC back-end | Clifford Wolf | 2017-09-29 | 2 | -0/+191 |
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* | Fix synth_ice40 doc regarding -top default | Clifford Wolf | 2017-09-29 | 1 | -1/+1 |
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* | Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted. | Andrew Zonenberg | 2017-09-14 | 2 | -2/+4 |
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* | Initial support for extraction of counters with clock enable | Andrew Zonenberg | 2017-09-14 | 1 | -21/+65 |
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* | Merge pull request #406 from azonenberg/coolrunner-techmap | Clifford Wolf | 2017-09-02 | 2 | -18/+125 |
|\ | | | | | Coolrunner techmapping improvements | ||||
| * | coolrunner2: Finish fixing special-use p-terms | Robert Ou | 2017-09-01 | 1 | -8/+20 |
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| * | coolrunner2: Generate a feed-through AND term when necessary | Robert Ou | 2017-09-01 | 1 | -13/+31 |
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| * | coolrunner2: Initial fixes for special p-terms | Robert Ou | 2017-09-01 | 2 | -1/+81 |
| | | | | | | | | | | Certain signals can only be controlled by a product term and not a sum-of-products. Do the initial work for fixing this. | ||||
| * | coolrunner2: Fix mapping of flip-flops | Robert Ou | 2017-09-01 | 1 | -1/+0 |
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| * | coolrunner2: Combine some for loops together | Robert Ou | 2017-09-01 | 1 | -16/+14 |
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* | | Fixed typo in error message | Andrew Zonenberg | 2017-09-01 | 1 | -1/+1 |
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* | | Added blackbox $__COUNT_ cell model | Andrew Zonenberg | 2017-09-01 | 2 | -0/+18 |
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* | | Refactoring: moved modules still in cells_sim to cells_sim_wip | Andrew Zonenberg | 2017-09-01 | 3 | -136/+138 |
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