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* Fix cells_sim.v for Achronix FPGAMiodrag Milanovic2019-01-041-1/+1
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* Merge pull request #755 from Icenowy/anlogic-dram-initClifford Wolf2019-01-026-2/+96
|\ | | | | anlogic: implement DRAM initialization
| * anlogic: implement DRAM initializationIcenowy Zheng2018-12-206-2/+96
| | | | | | | | | | | | | | | | | | | | | | As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-022-14/+15
|\ \ | | | | | | Initialization of Anlogic DFFs
| * | anlogic: set the init value of DFFsIcenowy Zheng2018-12-182-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As dffinit has already supported for different initialization strings for DFFs and check for re-initialization, initialization of Anlogic DFFs are now ready to go. Support for set the init values of Anlogic DFFs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | | Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-022-7/+41
|\ \ \ | | | | | | | | synth: add k-LUT mode
| * | | synth_ice40: use 4-LUT coarse synthesis mode.whitequark2019-01-021-1/+1
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| * | | synth: add k-LUT mode.whitequark2019-01-021-2/+36
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| * | | synth: improve script documentation. NFC.whitequark2019-01-021-6/+6
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* | | | Merge pull request #771 from whitequark/techmap_cmp2lutClifford Wolf2019-01-022-1/+106
|\| | | | | | | | | | | cmp2lut: new techmap pass
| * | | cmp2lut: new techmap pass.whitequark2019-01-022-1/+106
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* | | | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-0215-22/+22
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* | | Merge pull request #766 from Icenowy/anlogic-latchesClifford Wolf2018-12-311-0/+12
|\ \ \ | | | | | | | | anlogic: add latch cells
| * | | anlogic: add latch cellsIcenowy Zheng2018-12-251-0/+12
| | |/ | |/| | | | | | | | | | | | | | | | Add latch cells to Anlogic cells replacement library by copying other FPGAs' latch code to it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* / | Fix 7 instances of add_share_file to add_gen_share_fileLarry Doolittle2018-12-291-8/+8
|/ / | | | | | | in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
* | Merge pull request #752 from Icenowy/anlogic-lut-costClifford Wolf2018-12-191-1/+1
|\ \ | | | | | | Anlogic: let LUT5/6 have more cost than LUT4-
| * | Anlogic: let LUT5/6 have more cost than LUT4-Icenowy Zheng2018-12-191-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s. So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost 2x resource of a LUT5. Change the -lut parameter passed to the abc command to pass this cost info to the ABC process. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Merge pull request #753 from Icenowy/anlogic-makefile-fixClifford Wolf2018-12-191-0/+1
|\ \ | | | | | | anlogic: fix Makefile.inc
| * | anlogic: fix Makefile.incIcenowy Zheng2018-12-191-0/+1
| |/ | | | | | | | | | | | | | | | | During the addition of DRAM inferring support, the installation of eagle_bb.v is accidentally removed. Fix this issue. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* / anlogic: fix dbits of Anlogic Eagle DRAM16X4Icenowy Zheng2018-12-181-1/+1
|/ | | | | | | | | The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM bits. Fix the dbits number in the RAM configuration. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* anlogic: add support for Eagle Distributed RAMIcenowy Zheng2018-12-174-1/+43
| | | | | | | | | | | | | The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Revert "Leave only real black box cells"Icenowy Zheng2018-12-171-0/+312
| | | | | | | | | | | This reverts commit 43030db5fff285de85096aaf5578b0548659f6b7. For a synthesis tool, generating EG_LOGIC cells are a good choice, as they can be furtherly optimized when PnR, although sometimes EG_LOGIC is not as blackbox as EG_PHY cells (because the latter is more close to the hardware implementation). Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Rename "fine:" label to "map:" in "synth_ice40"Clifford Wolf2018-12-161-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-161-0/+2
|\ | | | | equiv_opt: new command, for verifying optimization passes
| * equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-071-0/+2
| | | | | | | | | | This allows avoiding techmap crashes e.g. because of large memories in white-box cell models.
* | Merge pull request #730 from smunaut/ffssr_dont_touchClifford Wolf2018-12-161-0/+3
|\ \ | | | | | | ice40: Honor the "dont_touch" attribute in FFSSR pass
| * | ice40: Honor the "dont_touch" attribute in FFSSR passSylvain Munaut2018-12-081-0/+3
| |/ | | | | | | | | | | | | This is useful if you want to place FF manually ... can't merge SR in those because it might make the manual placement invalid Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #725 from olofk/ram4k-initClifford Wolf2018-12-161-0/+19
|\ \ | | | | | | Only use non-blocking assignments of SB_RAM40_4K for yosys
| * | Only use non-blocking assignments of SB_RAM40_4K for yosysOlof Kindgren2018-12-061-0/+19
| |/ | | | | | | | | | | | | | | | | | | | | In an initial statement, blocking assignments are normally used and e.g. verilator throws a warning if non-blocking ones are used. Yosys cannot however properly resolve the interdependencies if blocking assignments are used in the initialization of SB_RAM_40_4K and thus this has been used. This patch will change to use non-blocking assignments only for yosys
* / synth_ice40: split `map_gates` off `fine`.whitequark2018-12-061-0/+4
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* synth_ice40: add -noabc option, to use built-in LUT techmapping.whitequark2018-12-051-2/+16
| | | | This should be combined with -relut to get sensible results.
* gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-052-0/+88
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* Fix typo.whitequark2018-12-051-2/+2
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* Merge pull request #713 from Diego-HR/masterClifford Wolf2018-12-055-12/+91
|\ | | | | Changes in GoWin synth commands and ALU primitive support
| * Changes in GoWin synth commands and ALU primitive supportDiego H2018-12-035-12/+91
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* | Merge pull request #712 from mmicko/anlogic-supportClifford Wolf2018-12-057-0/+1278
|\ \ | | | | | | Initial support for Anlogic FPGA
| * | Leave only real black box cellsMiodrag Milanovic2018-12-021-312/+0
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| * | Initial support for Anlogic FPGAMiodrag Milanovic2018-12-017-0/+1590
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* | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-2/+2
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* | synth_ice40: add -relut option, to run ice40_unlut and opt_lut.whitequark2018-12-051-1/+13
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* | Extract ice40_unlut pass from ice40_opt.whitequark2018-12-053-13/+109
| | | | | | | | | | | | | | | | Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert them back to logic immediately. This is not desirable if the goal is to operate on $lut cells. If this is desirable, the same result as `ice40_opt -unlut` can be achieved by running simplemap and opt after ice40_unlut.
* | ice40: Add option to only use CE if it'd be use by more than X FFsSylvain Munaut2018-11-271-0/+14
|/ | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Merge pull request #697 from eddiehung/xilinx_ps7Clifford Wolf2018-11-122-0/+624
|\ | | | | Add support for PS7 block for Xilinx
| * Add support for Xilinx PS7 blockEddie Hung2018-11-102-0/+624
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* | Merge pull request #695 from daveshah1/ecp5_bbClifford Wolf2018-11-122-1/+420
|\ \ | |/ |/| ecp5: Adding some blackbox cells
| * ecp5: Add 'fake' DCU parametersDavid Shah2018-11-091-0/+11
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Add blackboxes for ancillary DCU cellsDavid Shah2018-11-091-0/+18
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Adding some blackbox cellsDavid Shah2018-11-072-1/+391
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fix sf2 LUT interfaceClifford Wolf2018-10-312-12/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Basic SmartFusion2 and IGLOO2 synthesis supportClifford Wolf2018-10-315-0/+377
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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