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* | | Merge pull request #2226 from YosysHQ/mwk/nuke-efinix-gbuf | Miodrag Milanović | 2020-07-16 | 5 | -122/+11 | |
|\ \ | | | | | | | efinix: Nuke efinix_gbuf in favor of clkbufmap. | |||||
| * | | efinix: Nuke efinix_gbuf in favor of clkbufmap. | Marcelina Kościelnicka | 2020-07-04 | 5 | -122/+11 | |
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* | | | achronix: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-14 | 1 | -1/+1 | |
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* | | | intel: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-13 | 8 | -178/+17 | |
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* | | | Revert "intel_alm: direct M10K instantiation" | Lofty | 2020-07-13 | 7 | -122/+38 | |
| | | | | | | | | | | | | This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67. | |||||
* | | | xilinx: Fix srl regression. | Marcelina Kościelnicka | 2020-07-12 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly. | |||||
* | | | sf2: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-09 | 2 | -44/+13 | |
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* | | | xilinx: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-09 | 6 | -484/+131 | |
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* | | | efinix: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-06 | 2 | -15/+53 | |
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* | | | gowin: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-06 | 2 | -145/+41 | |
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* | | | intel_alm: direct M10K instantiation | Dan Ravensloft | 2020-07-05 | 7 | -38/+122 | |
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* | | | synth_gowin: ABC9 support | Dan Ravensloft | 2020-07-05 | 2 | -34/+340 | |
| | | | | | | | | | | | | | | | This adds ABC9 support for synth_gowin; drastically improving synthesis quality. | |||||
* | | | Merge pull request #2236 from YosysHQ/mwk/dfflegalize-ice40 | Marcelina Kościelnicka | 2020-07-05 | 4 | -208/+24 | |
|\ \ \ | | | | | | | | | ice40: Use dfflegalize. | |||||
| * | | | ice40: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-05 | 4 | -208/+24 | |
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* | | | | ecp5: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-05 | 4 | -254/+96 | |
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* | | | | Merge pull request #2232 from YosysHQ/mwk/gowin-sim-init | Marcelina Kościelnicka | 2020-07-05 | 1 | -8/+8 | |
|\ \ \ \ | | | | | | | | | | | gowin: Fix INIT values in sim library. | |||||
| * | | | | gowin: Fix INIT values in sim library. | Marcelina Kościelnicka | 2020-07-05 | 1 | -8/+8 | |
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* | | | | intel_alm: DSP inference | Dan Ravensloft | 2020-07-05 | 6 | -9/+186 | |
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* | | | gowin: replace determine_init with setundef | Dan Ravensloft | 2020-07-04 | 3 | -74/+1 | |
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* | | | synth_intel_alm: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-04 | 2 | -121/+9 | |
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* | | Improve MISTRAL_FF specify rules | Dan Ravensloft | 2020-07-04 | 1 | -5/+4 | |
| | | | | | | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com> | |||||
* | | intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF | Eddie Hung | 2020-07-04 | 2 | -47/+2 | |
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* | | intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY | Eddie Hung | 2020-07-04 | 4 | -4/+4 | |
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* | | intel_alm: ABC9 sequential optimisations | Dan Ravensloft | 2020-07-04 | 7 | -19/+149 | |
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* | simcells: Fix reset polarity for $_DLATCH_???_ cells. | Marcelina Kościelnicka | 2020-06-30 | 2 | -5/+5 | |
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* | Update dff2dffe, dff2dffs, zinit to new FF types. | Marcelina Kościelnicka | 2020-06-23 | 16 | -128/+128 | |
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* | Add new FF types to simplemap. | Marcelina Kościelnicka | 2020-06-23 | 1 | -1/+1 | |
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* | Add new builtin FF types | Marcelina Kościelnicka | 2020-06-23 | 3 | -0/+2293 | |
| | | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits). | |||||
* | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 31 | -95/+95 | |
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* | Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH | Xark | 2020-06-14 | 1 | -7/+7 | |
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* | intel_alm: fix DFFE matching | Dan Ravensloft | 2020-06-11 | 1 | -1/+1 | |
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* | Do not optimize away FFs in "prep" and Verific fron-end | Claire Wolf | 2020-06-09 | 1 | -2/+2 | |
| | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
* | Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve | Eddie Hung | 2020-06-04 | 1 | -1/+1 | |
|\ | | | | | abc9: -dff improvements | |||||
| * | abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ | Eddie Hung | 2020-05-29 | 1 | -1/+1 | |
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* | | Add flooring division operator | Xiretza | 2020-05-28 | 2 | -0/+71 | |
| | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor. | |||||
* | | Add flooring modulo operator | Xiretza | 2020-05-28 | 2 | -3/+124 | |
| | | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor. | |||||
* | | xilinx: tidy up cells_sim.v a little | Eddie Hung | 2020-05-25 | 1 | -5/+7 | |
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* | ecp5: cleanup unused +/ecp5/abc9_model.v | Eddie Hung | 2020-05-23 | 3 | -14/+0 | |
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* | Add force_downto and force_upto wire attributes. | Marcelina Kościelnicka | 2020-05-19 | 39 | -24/+232 | |
| | | | | Fixes #2058. | |||||
* | abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ | Eddie Hung | 2020-05-14 | 2 | -14/+2 | |
| | | | | instead of moving them to $__ prefix | |||||
* | abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it | Eddie Hung | 2020-05-14 | 2 | -5/+4 | |
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* | abc9_ops/xaiger: further reducing Module::derive() calls by ... | Eddie Hung | 2020-05-14 | 2 | -7/+5 | |
| | | | | replacing _all_ (* abc9_box *) instantiations with their derived types | |||||
* | Cleanup; reduce Module::derive() calls | Eddie Hung | 2020-05-14 | 2 | -4/+4 | |
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* | ecp5: latches_map.v if *not* -asyncprld | Eddie Hung | 2020-05-14 | 1 | -2/+2 | |
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* | ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v | Eddie Hung | 2020-05-14 | 4 | -43/+3 | |
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* | ecp5: fix rebase mistake | Eddie Hung | 2020-05-14 | 1 | -3/+3 | |
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* | xilinx: gate specify/attributes from iverilog | Eddie Hung | 2020-05-14 | 1 | -1/+3 | |
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* | abc9: only do +/abc9_map if `DFF | Eddie Hung | 2020-05-14 | 1 | -0/+2 | |
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* | ecp5: TRELLIS_FF bypass path only in async mode | Eddie Hung | 2020-05-14 | 1 | -8/+8 | |
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* | xilinx/ice40/ecp5: zinit requires selected wires, so select them all | Eddie Hung | 2020-05-14 | 3 | -4/+4 | |
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