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* | | xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-121-2/+2
| | | | | | | | | | | | | | | | | | | | | Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly.
* | | sf2: Use dfflegalize.Marcelina Kościelnicka2020-07-092-44/+13
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* | | xilinx: Use dfflegalize.Marcelina Kościelnicka2020-07-096-484/+131
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* | | efinix: Use dfflegalize.Marcelina Kościelnicka2020-07-062-15/+53
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* | | gowin: Use dfflegalize.Marcelina Kościelnicka2020-07-062-145/+41
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* | | intel_alm: direct M10K instantiationDan Ravensloft2020-07-057-38/+122
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* | | synth_gowin: ABC9 supportDan Ravensloft2020-07-052-34/+340
| | | | | | | | | | | | | | | This adds ABC9 support for synth_gowin; drastically improving synthesis quality.
* | | Merge pull request #2236 from YosysHQ/mwk/dfflegalize-ice40Marcelina Kościelnicka2020-07-054-208/+24
|\ \ \ | | | | | | | | ice40: Use dfflegalize.
| * | | ice40: Use dfflegalize.Marcelina Kościelnicka2020-07-054-208/+24
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* | | | ecp5: Use dfflegalize.Marcelina Kościelnicka2020-07-054-254/+96
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* | | | Merge pull request #2232 from YosysHQ/mwk/gowin-sim-initMarcelina Kościelnicka2020-07-051-8/+8
|\ \ \ \ | | | | | | | | | | gowin: Fix INIT values in sim library.
| * | | | gowin: Fix INIT values in sim library.Marcelina Kościelnicka2020-07-051-8/+8
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* | | | intel_alm: DSP inferenceDan Ravensloft2020-07-056-9/+186
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* | | gowin: replace determine_init with setundefDan Ravensloft2020-07-043-74/+1
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* | | synth_intel_alm: Use dfflegalize.Marcelina Kościelnicka2020-07-042-121/+9
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* | Improve MISTRAL_FF specify rulesDan Ravensloft2020-07-041-5/+4
| | | | | | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* | intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FFEddie Hung2020-07-042-47/+2
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* | intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLYEddie Hung2020-07-044-4/+4
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* | intel_alm: ABC9 sequential optimisationsDan Ravensloft2020-07-047-19/+149
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* simcells: Fix reset polarity for $_DLATCH_???_ cells.Marcelina Kościelnicka2020-06-302-5/+5
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* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-2316-128/+128
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* Add new FF types to simplemap.Marcelina Kościelnicka2020-06-231-1/+1
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* Add new builtin FF typesMarcelina Kościelnicka2020-06-233-0/+2293
| | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits).
* Use C++11 final/override keywords.whitequark2020-06-1831-95/+95
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* Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTHXark2020-06-141-7/+7
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* intel_alm: fix DFFE matchingDan Ravensloft2020-06-111-1/+1
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* Do not optimize away FFs in "prep" and Verific fron-endClaire Wolf2020-06-091-2/+2
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-1/+1
|\ | | | | abc9: -dff improvements
| * abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_Eddie Hung2020-05-291-1/+1
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* | Add flooring division operatorXiretza2020-05-282-0/+71
| | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* | Add flooring modulo operatorXiretza2020-05-282-3/+124
| | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* | xilinx: tidy up cells_sim.v a littleEddie Hung2020-05-251-5/+7
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* ecp5: cleanup unused +/ecp5/abc9_model.vEddie Hung2020-05-233-14/+0
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-1939-24/+232
| | | | Fixes #2058.
* abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_Eddie Hung2020-05-142-14/+2
| | | | instead of moving them to $__ prefix
* abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove itEddie Hung2020-05-142-5/+4
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* abc9_ops/xaiger: further reducing Module::derive() calls by ...Eddie Hung2020-05-142-7/+5
| | | | replacing _all_ (* abc9_box *) instantiations with their derived types
* Cleanup; reduce Module::derive() callsEddie Hung2020-05-142-4/+4
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* ecp5: latches_map.v if *not* -asyncprldEddie Hung2020-05-141-2/+2
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* ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.vEddie Hung2020-05-144-43/+3
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* ecp5: fix rebase mistakeEddie Hung2020-05-141-3/+3
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* xilinx: gate specify/attributes from iverilogEddie Hung2020-05-141-1/+3
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* abc9: only do +/abc9_map if `DFFEddie Hung2020-05-141-0/+2
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* ecp5: TRELLIS_FF bypass path only in async modeEddie Hung2020-05-141-8/+8
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* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-143-4/+4
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* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-143-4/+198
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* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-148-763/+129
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-142-10/+26
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* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-144-4/+3
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* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-144-0/+55
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