iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix spacing	Eddie Hung	2019-04-16	1	-1/+1
*	Make cells.box whiteboxes not blackboxes	Eddie Hung	2019-04-16	1	-2/+2
*	read_verilog cells_box.v before techmap	Eddie Hung	2019-04-16	1	-1/+1
*	synth_xilinx: before abc read +/xilinx/cells_box.v	Eddie Hung	2019-04-16	1	-0/+1
*	Add +/xilinx/cells_box.v containing models for ABC boxes	Eddie Hung	2019-04-16	2	-0/+11
*	Revert "Add abc_box_id attribute to MUXF7/F8 cells"	Eddie Hung	2019-04-16	1	-2/+0
*	Add abc_box_id attribute to MUXF7/F8 cells	Eddie Hung	2019-04-15	1	-0/+2
*	Merge branch 'xaig' into xc7mux	Eddie Hung	2019-04-15	3	-41/+60
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\| *	Add support for synth_xilinx -abc9 and ignore abc9 -dress opt	Eddie Hung	2019-04-12	1	-1/+9
\| *	Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.	Keith Rothman	2019-04-12	3	-52/+14
\| *	Fix LUT6_2 definition.	Keith Rothman	2019-04-09	1	-3/+3
\| *	Add additional cells sim models for core 7-series primatives.	Keith Rothman	2019-04-09	1	-0/+57
* \|	Fix cells_map.v some more	Eddie Hung	2019-04-11	1	-7/+7
* \|	More fine tuning	Eddie Hung	2019-04-11	1	-2/+2
* \|	Fix cells_map.v	Eddie Hung	2019-04-11	1	-7/+7
* \|	Fix typo	Eddie Hung	2019-04-11	1	-1/+1
* \|	Juggle opt calls in synth_xilinx	Eddie Hung	2019-04-11	2	-30/+35
* \|	WIP for cells_map.v -- maybe working?	Eddie Hung	2019-04-10	1	-32/+27
* \|	Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1	Eddie Hung	2019-04-10	1	-31/+38
* \|	Fix for when B_SIGNED = 1	Eddie Hung	2019-04-10	1	-1/+8
* \|	Update doc for synth_xilinx	Eddie Hung	2019-04-10	1	-7/+8
* \|	ff_map.v after abc	Eddie Hung	2019-04-10	1	-5/+5
* \|	Tidy up	Eddie Hung	2019-04-10	1	-1/+1
* \|	Move map_cells to before map_luts	Eddie Hung	2019-04-10	1	-11/+12
* \|	WIP for $shiftx to wide mux	Eddie Hung	2019-04-10	1	-1/+63
* \|	Update LUT delays	Eddie Hung	2019-04-10	1	-11/+8
* \|	Add cells.lut to techlibs/xilinx/	Eddie Hung	2019-04-09	2	-0/+16
* \|	synth_xilinx to call abc with -lut +/xilinx/cells.lut	Eddie Hung	2019-04-09	1	-2/+2
* \|	Add delays to cells.box	Eddie Hung	2019-04-09	1	-4/+12
* \|	synth_xilinx with abc9 to use -box	Eddie Hung	2019-04-09	1	-1/+4
* \|	Add techlibs/xilinx/cells.box	Eddie Hung	2019-04-09	2	-0/+6
* \|	Add support for synth_xilinx -abc9 and ignore abc9 -dress opt	Eddie Hung	2019-04-09	1	-1/+9
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*	xilinx: Add keep attribute where appropriate	David Shah	2019-03-22	2	-25/+31
*	Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873	Clifford Wolf	2019-03-19	1	-2/+4
*	Merge pull request #842 from litghost/merge_upstream	Clifford Wolf	2019-03-05	10	-176/+570
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\| *	Revert BRAM WRITE_MODE changes.	Keith Rothman	2019-03-04	1	-12/+12
\| *	Revert FF models to include IS_x_INVERTED parameters.	Keith Rothman	2019-03-01	1	-6/+34
\| *	Use singular for disabling of DRAM or BRAM inference.	Keith Rothman	2019-03-01	1	-13/+13
\| *	Modify arguments to match existing style.	Keith Rothman	2019-03-01	1	-6/+6
\| *	Changes required for VPR place and route synth_xilinx.	Keith Rothman	2019-03-01	11	-221/+587
* \|	Use "write_edif -pvector bra" for Xilinx EDIF files	Clifford Wolf	2019-03-05	1	-1/+1
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*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	1	-1/+1
*	Add support for Xilinx PS7 block	Eddie Hung	2018-11-10	2	-0/+624
*	xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.	Tim 'mithro' Ansell	2018-10-08	1	-3/+2
*	Add inout ports to cells_xtra.v	Clifford Wolf	2018-10-04	2	-2/+14
*	xilinx: Adding missing inout IO port to IOBUF	Tim Ansell	2018-10-03	1	-0/+1
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Improving vpr output support.	Tim 'mithro' Ansell	2018-04-18	2	-3/+36
*	Squelch trailing whitespace, including meta-whitespace	Larry Doolittle	2018-03-11	1	-8/+8
*	Add Xilinx RAM64X1D and RAM128X1D simulation models	Clifford Wolf	2018-03-07	4	-23/+30