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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-04 11:30:55 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-10-04 11:30:55 +0200 |
| commit | 5f1fea08d5e14ecaa1cf60eb865c60132a0ce3e1 (patch) | |
| tree | 0e4d9990883c1d07549426916d5c0cb6119ebb5c /techlibs/xilinx | |
| parent | bed6c26a6e3d12750dc59d8db1cd4a909699a202 (diff) | |
| download | yosys-5f1fea08d5e14ecaa1cf60eb865c60132a0ce3e1.tar.gz yosys-5f1fea08d5e14ecaa1cf60eb865c60132a0ce3e1.tar.bz2 yosys-5f1fea08d5e14ecaa1cf60eb865c60132a0ce3e1.zip | |
Add inout ports to cells_xtra.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.sh | 4 | ||||
| -rw-r--r-- | techlibs/xilinx/cells_xtra.v | 12 |
2 files changed, 14 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh index c7ad16043..e7c7d17bf 100644 --- a/techlibs/xilinx/cells_xtra.sh +++ b/techlibs/xilinx/cells_xtra.sh @@ -1,13 +1,13 @@ #!/bin/bash set -e -libdir="/opt/Xilinx/Vivado/2015.4/data/verilog/src" +libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src" function xtract_cell_decl() { for dir in $libdir/xeclib $libdir/retarget; do [ -f $dir/$1.v ] || continue - egrep '^\s*((end)?module|parameter|input|output|(end)?function|(end)?task)' $dir/$1.v | + egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v | sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d; s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/; s/\s+$//; s/,$/;/; /input|output|parameter/ s/[^;]$/&;/; s/\s+/ /g; diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index f5abf3ae0..69e54233a 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -2237,6 +2237,7 @@ module IOBUF_DCIEN (...); parameter SLEW = "SLOW"; parameter USE_IBUFDISABLE = "TRUE"; output O; + inout IO; input DCITERMDISABLE; input I; input IBUFDISABLE; @@ -2251,6 +2252,7 @@ module IOBUF_INTERMDISABLE (...); parameter SLEW = "SLOW"; parameter USE_IBUFDISABLE = "TRUE"; output O; + inout IO; input I; input IBUFDISABLE; input INTERMDISABLE; @@ -2264,6 +2266,7 @@ module IOBUFDS (...); parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; output O; + inout IO, IOB; input I, T; endmodule @@ -2276,6 +2279,8 @@ module IOBUFDS_DCIEN (...); parameter SLEW = "SLOW"; parameter USE_IBUFDISABLE = "TRUE"; output O; + inout IO; + inout IOB; input DCITERMDISABLE; input I; input IBUFDISABLE; @@ -2289,6 +2294,8 @@ module IOBUFDS_DIFF_OUT (...); parameter IOSTANDARD = "DEFAULT"; output O; output OB; + inout IO; + inout IOB; input I; input TM; input TS; @@ -2303,6 +2310,8 @@ module IOBUFDS_DIFF_OUT_DCIEN (...); parameter USE_IBUFDISABLE = "TRUE"; output O; output OB; + inout IO; + inout IOB; input DCITERMDISABLE; input I; input IBUFDISABLE; @@ -2319,6 +2328,8 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); parameter USE_IBUFDISABLE = "TRUE"; output O; output OB; + inout IO; + inout IOB; input I; input IBUFDISABLE; input INTERMDISABLE; @@ -2382,6 +2393,7 @@ module ISERDESE2 (...); endmodule module KEEPER (...); + inout O; endmodule module LDCE (...); |