aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx
Commit message (Expand)AuthorAgeFilesLines
* Fix name clashEddie Hung2019-06-131-4/+8
* Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-06-121-0/+8
* Reduce diff with masterEddie Hung2019-06-121-1/+1
* Fix spacingEddie Hung2019-06-121-6/+6
* Remove wide mux inferenceEddie Hung2019-06-124-194/+3
* Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-1/+1
* Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-1/+1
* Add "-W' wire delay arg to abc9, use from synth_xilinxEddie Hung2019-06-111-1/+1
* Disable dist RAM boxes due to comb loopEddie Hung2019-06-111-2/+2
* Remove #ifndef ABCEddie Hung2019-06-111-4/+0
* Revert "Revert "Move ff_map back after ABC for shregmap""Eddie Hung2019-06-101-5/+5
* Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"Eddie Hung2019-06-101-2/+2
* Comment out muxpack (currently broken)Eddie Hung2019-06-071-2/+2
* $__XILINX_MUX_ -> $__XILINX_SHIFTXEddie Hung2019-06-062-11/+11
* Fix muxcover and its techmappingEddie Hung2019-06-062-3/+3
* Run muxpack and muxcover in synth_xilinxEddie Hung2019-06-062-1/+18
* Remove abc_flop attributes for nowEddie Hung2019-06-061-56/+10
* Update abc attributes on FD*E_1Eddie Hung2019-06-051-6/+26
* CleanupEddie Hung2019-06-052-17/+0
* Call shregmap -tech xilinx_staticEddie Hung2019-06-051-1/+1
* Revert "Move ff_map back after ABC for shregmap"Eddie Hung2019-06-051-4/+4
* Rename shregmap -tech xilinx -> xilinx_dynamicEddie Hung2019-06-041-2/+2
* Add space between -D and _ABCEddie Hung2019-06-041-2/+2
* Add (* abc_flop_q *) to brams_bb.vEddie Hung2019-06-041-8/+8
* Fix name clashEddie Hung2019-06-041-11/+11
* Add mux_map.v for wide muxEddie Hung2019-06-044-30/+82
* Move ff_map back after ABC for shregmapEddie Hung2019-06-031-4/+4
* Respect -nocarryEddie Hung2019-06-031-1/+3
* Fix pmux2shiftx logicEddie Hung2019-06-031-1/+1
* Merge mistakeEddie Hung2019-06-031-14/+6
* Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-031-1/+5
|\
| * Remove extra newlineEddie Hung2019-06-031-1/+0
| * Execute techmap and arith_map simultaneouslyEddie Hung2019-06-031-6/+6
* | TypoEddie Hung2019-06-031-1/+1
* | IS_C_INVERTEDEddie Hung2019-06-031-4/+4
* | Fix `ifndefEddie Hung2019-06-031-1/+1
* | Add flops as blackboxesEddie Hung2019-05-312-0/+27
* | Add FD*E_1 -> FD*E techmap rulesEddie Hung2019-05-311-5/+31
* | Techmap flops before ABC againEddie Hung2019-05-311-4/+4
* | Merge branch 'xaig' into xc7muxEddie Hung2019-05-311-0/+1
|\ \
| * \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-226-36/+222
| |\ \
| * \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-221-8/+10
| |\ \ \
| * \ \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-202-10/+12
| |\ \ \ \
* | | | | | Remove whitebox attribute from DRAMs for nowEddie Hung2019-05-301-2/+2
* | | | | | Carry in/out to be the last input/output for chains to be preservedEddie Hung2019-05-302-12/+15
* | | | | | Some more realistic delays...Eddie Hung2019-05-291-7/+7
* | | | | | TypoEddie Hung2019-05-281-1/+1
* | | | | | Make MUXF{7,8} and CARRY4 whiteboxEddie Hung2019-05-271-3/+3
* | | | | | Re-enable lib_whiteboxEddie Hung2019-05-271-5/+5
* | | | | | BlackboxesEddie Hung2019-05-262-10/+10