| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0 | Eddie Hung | 2020-01-22 | 1 | -1/+1 |
| * | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor | Eddie Hung | 2020-01-21 | 2 | -125/+88 |
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| | * | Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623 | Eddie Hung | 2020-01-17 | 2 | -119/+82 |
| | * | +/xilinx/arith_map.v fix $lcu rule | Eddie Hung | 2020-01-17 | 1 | -6/+6 |
| * | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor | Eddie Hung | 2020-01-15 | 1 | -1/+1 |
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| | * | Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W | Miodrag Milanović | 2020-01-15 | 1 | -1/+1 |
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| | | * | synth_xilinx: fix default W value for non-xc7 | Eddie Hung | 2020-01-14 | 1 | -1/+1 |
| * | | | Adding (* techmap_autopurge *) to FD* in abc9_map.v | Eddie Hung | 2020-01-14 | 1 | -8/+8 |
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| * | | Merge pull request #1623 from YosysHQ/mmicko/edif_attr | Miodrag Milanović | 2020-01-14 | 1 | -1/+1 |
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| | * | Use CARRY4 for abc1 as well, preventing issues with Vivado | Miodrag Milanovic | 2020-01-10 | 1 | -1/+1 |
| * | | Another conflict | Eddie Hung | 2020-01-11 | 1 | -1/+0 |
| * | | synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro | Eddie Hung | 2020-01-10 | 1 | -4/+11 |
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| * | Fix abc9_xc7.box comments | Eddie Hung | 2020-01-07 | 1 | -7/+14 |
| * | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2020-01-06 | 6 | -152/+642 |
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| | * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-06 | 5 | -1674/+509 |
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| | * | | Fix spacing | Eddie Hung | 2020-01-02 | 1 | -1/+1 |
| | * | | synth_xilinx -dff to work with abc too | Eddie Hung | 2020-01-02 | 1 | -6/+14 |
| | * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-02 | 2 | -24/+44 |
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| | * | | | Update comments | Eddie Hung | 2020-01-02 | 1 | -11/+6 |
| | * | | | abc9 -keepff -> -dff; refactor dff operations | Eddie Hung | 2020-01-02 | 2 | -58/+58 |
| | * | | | Clamp -46ps for FDPE* too | Eddie Hung | 2020-01-01 | 1 | -2/+2 |
| | * | | | Restore abc9 -keepff | Eddie Hung | 2020-01-01 | 2 | -86/+6 |
| | * | | | Re-arrange FD order | Eddie Hung | 2019-12-31 | 3 | -182/+182 |
| | * | | | Cleanup xilinx boxes | Eddie Hung | 2019-12-31 | 2 | -391/+425 |
| | * | | | Update abc9_xc7.box comments | Eddie Hung | 2019-12-31 | 1 | -18/+18 |
| | * | | | FDCE ports to be alphabetical | Eddie Hung | 2019-12-31 | 1 | -3/+3 |
| | * | | | Fix attributes on $__ABC9_ASYNC[01] whitebox | Eddie Hung | 2019-12-31 | 1 | -2/+2 |
| | * | | | Fix incorrect $__ABC9_ASYNC[01] box | Eddie Hung | 2019-12-31 | 1 | -2/+2 |
| | * | | | Do not offset FD* box timings due to -46ps Tsu | Eddie Hung | 2019-12-30 | 1 | -12/+21 |
| | * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-30 | 8 | -21/+374 |
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| | * | | | | Tidy up abc9_map.v | Eddie Hung | 2019-12-30 | 1 | -103/+103 |
| | * | | | | Add "synth_xilinx -dff" option, cleanup abc9 | Eddie Hung | 2019-12-30 | 2 | -2/+98 |
| | * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 1 | -24/+10 |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 4 | -172/+240 |
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| | * | | | | | | Add RAM{32,64}M to abc9_map.v | Eddie Hung | 2019-12-19 | 1 | -0/+78 |
| | * | | | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t | Eddie Hung | 2019-12-19 | 5 | -36/+55 |
| | * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-19 | 12 | -77/+967 |
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| | * | | | | | | | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 |
| | * | | | | | | | Fix comment | Eddie Hung | 2019-12-09 | 1 | -1/+1 |
| | * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 5 | -633/+868 |
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| | * | | | | | | | | Remove creation of $abc9_control_wire | Eddie Hung | 2019-12-06 | 1 | -16/+6 |
| | * | | | | | | | | abc9 to use mergeability class to differentiate sync/async | Eddie Hung | 2019-12-06 | 1 | -12/+15 |
| | * | | | | | | | | Remove clkpart | Eddie Hung | 2019-12-05 | 1 | -4/+0 |
| | * | | | | | | | | Revert "Special abc9_clock wire to contain only clock signal" | Eddie Hung | 2019-12-05 | 1 | -10/+12 |
| | * | | | | | | | | Missing wire declaration | Eddie Hung | 2019-12-04 | 1 | -0/+1 |
| | * | | | | | | | | abc9_map.v to transform INIT=1 to INIT=0 | Eddie Hung | 2019-12-04 | 1 | -118/+201 |
| | * | | | | | | | | Oh deary me | Eddie Hung | 2019-12-04 | 1 | -4/+4 |
| | * | | | | | | | | output reg Q -> output Q to suppress warning | Eddie Hung | 2019-12-04 | 1 | -8/+8 |
| | * | | | | | | | | abc9_map.v to do `zinit' and make INIT = 1'b0 | Eddie Hung | 2019-12-04 | 1 | -70/+112 |
| | * | | | | | | | | Add abc9_init wire, attach to abc9_flop cell | Eddie Hung | 2019-12-03 | 1 | -2/+12 |
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