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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-22 14:22:03 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-22 14:22:03 -0800 |
| commit | da134701cd86e3958490b97fd6d840ce24586080 (patch) | |
| tree | 1c8af32cf81ca3ae7f34f5bb244dd2f422bdbd9c /techlibs/xilinx | |
| parent | 73526a6f103c927dd0d1504281659a87e7943688 (diff) | |
| download | yosys-da134701cd86e3958490b97fd6d840ce24586080.tar.gz yosys-da134701cd86e3958490b97fd6d840ce24586080.tar.bz2 yosys-da134701cd86e3958490b97fd6d840ce24586080.zip | |
Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/abc9_model.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index 204fa883f..15d12c89f 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -42,7 +42,7 @@ endmodule // Box to emulate async behaviour of FDP* (* abc9_box_id = 1001, lib_whitebox *) module \$__ABC9_ASYNC1 (input A, S, output Y); - assign Y = S ? 1'b0 : A; + assign Y = S ? 1'b1 : A; endmodule // Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32} |