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Author
Age
Files
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synth_xilinx: cleanup help
Eddie Hung
2020-01-28
1
-6
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+4
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synth_xilinx: fix help when no active_design; fixes #1664
Eddie Hung
2020-01-28
1
-2
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+3
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xilinx: Add simulation model for DSP48 (Virtex 4).
Marcin Kościelnicki
2020-01-29
6
-45
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+534
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Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
Eddie Hung
2020-01-28
1
-62
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+37
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xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
Eddie Hung
2020-01-27
1
-62
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+37
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Fix unresolved conflict from #1573
Eddie Hung
2020-01-28
1
-1
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+1
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Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
N. Engelhardt
2020-01-28
1
-0
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+3
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Duplicate tribuf call, credit to @mwkmwkmwk
Eddie Hung
2019-12-13
1
-1
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+0
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synth_xilinx: error out if tristate without '-iopad'
Eddie Hung
2019-12-12
1
-0
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+4
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Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
Eddie Hung
2020-01-22
1
-1
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+1
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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
Eddie Hung
2020-01-21
2
-125
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+88
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Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623
Eddie Hung
2020-01-17
2
-119
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+82
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+/xilinx/arith_map.v fix $lcu rule
Eddie Hung
2020-01-17
1
-6
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+6
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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
Eddie Hung
2020-01-15
1
-1
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+1
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Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W
Miodrag Milanović
2020-01-15
1
-1
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+1
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synth_xilinx: fix default W value for non-xc7
Eddie Hung
2020-01-14
1
-1
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+1
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Adding (* techmap_autopurge *) to FD* in abc9_map.v
Eddie Hung
2020-01-14
1
-8
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+8
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Merge pull request #1623 from YosysHQ/mmicko/edif_attr
Miodrag Milanović
2020-01-14
1
-1
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+1
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Use CARRY4 for abc1 as well, preventing issues with Vivado
Miodrag Milanovic
2020-01-10
1
-1
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+1
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Another conflict
Eddie Hung
2020-01-11
1
-1
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+0
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synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro
Eddie Hung
2020-01-10
1
-4
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+11
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Fix abc9_xc7.box comments
Eddie Hung
2020-01-07
1
-7
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+14
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Merge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung
2020-01-06
6
-152
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+642
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2020-01-06
5
-1674
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+509
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Fix spacing
Eddie Hung
2020-01-02
1
-1
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+1
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synth_xilinx -dff to work with abc too
Eddie Hung
2020-01-02
1
-6
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+14
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2020-01-02
2
-24
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+44
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Update comments
Eddie Hung
2020-01-02
1
-11
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+6
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abc9 -keepff -> -dff; refactor dff operations
Eddie Hung
2020-01-02
2
-58
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+58
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Clamp -46ps for FDPE* too
Eddie Hung
2020-01-01
1
-2
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+2
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Restore abc9 -keepff
Eddie Hung
2020-01-01
2
-86
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+6
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Re-arrange FD order
Eddie Hung
2019-12-31
3
-182
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+182
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Cleanup xilinx boxes
Eddie Hung
2019-12-31
2
-391
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+425
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Update abc9_xc7.box comments
Eddie Hung
2019-12-31
1
-18
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+18
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FDCE ports to be alphabetical
Eddie Hung
2019-12-31
1
-3
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+3
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Fix attributes on $__ABC9_ASYNC[01] whitebox
Eddie Hung
2019-12-31
1
-2
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+2
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Fix incorrect $__ABC9_ASYNC[01] box
Eddie Hung
2019-12-31
1
-2
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+2
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Do not offset FD* box timings due to -46ps Tsu
Eddie Hung
2019-12-30
1
-12
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+21
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-30
8
-21
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+374
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Tidy up abc9_map.v
Eddie Hung
2019-12-30
1
-103
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+103
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Add "synth_xilinx -dff" option, cleanup abc9
Eddie Hung
2019-12-30
2
-2
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+98
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-20
1
-24
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+10
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-20
4
-172
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+240
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Add RAM{32,64}M to abc9_map.v
Eddie Hung
2019-12-19
1
-0
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+78
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Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
Eddie Hung
2019-12-19
5
-36
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+55
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-19
12
-77
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+967
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abc9_map.v: fix Xilinx LUTRAM
Eddie Hung
2019-12-12
1
-6
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+6
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Fix comment
Eddie Hung
2019-12-09
1
-1
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+1
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-06
5
-633
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+868
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Remove creation of $abc9_control_wire
Eddie Hung
2019-12-06
1
-16
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+6
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