aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx
Commit message (Expand)AuthorAgeFilesLines
* Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
* Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
* Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
* xilinx: Add keep attribute where appropriateDavid Shah2019-03-222-25/+31
* Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
* Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-0510-176/+570
|\
| * Revert BRAM WRITE_MODE changes.Keith Rothman2019-03-041-12/+12
| * Revert FF models to include IS_x_INVERTED parameters.Keith Rothman2019-03-011-6/+34
| * Use singular for disabling of DRAM or BRAM inference.Keith Rothman2019-03-011-13/+13
| * Modify arguments to match existing style.Keith Rothman2019-03-011-6/+6
| * Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-0111-221/+587
* | Use "write_edif -pvector bra" for Xilinx EDIF filesClifford Wolf2019-03-051-1/+1
|/
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
* Add support for Xilinx PS7 blockEddie Hung2018-11-102-0/+624
* xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.Tim 'mithro' Ansell2018-10-081-3/+2
* Add inout ports to cells_xtra.vClifford Wolf2018-10-042-2/+14
* xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-031-0/+1
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Improving vpr output support.Tim 'mithro' Ansell2018-04-182-3/+36
* Squelch trailing whitespace, including meta-whitespaceLarry Doolittle2018-03-111-8/+8
* Add Xilinx RAM64X1D and RAM128X1D simulation modelsClifford Wolf2018-03-074-23/+30
* Add techlibs/xilinx/lut2lut.vClifford Wolf2017-07-102-0/+66
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Added black box modules for all the 7-series design elements (as listed in ug...Clifford Wolf2016-03-194-0/+3441
* Run dffsr2dff in synth_xilinxClifford Wolf2016-02-131-0/+2
* Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-011-2/+2
* Bugfix in Xilinx LUT mappingClifford Wolf2015-10-301-1/+1
* Added examples/ top-level directoryClifford Wolf2015-10-137-77/+0
* Added read-enable to memory modelClifford Wolf2015-09-253-19/+23
* Switched to Python 3Clifford Wolf2015-08-222-5/+2
* Another bugfix for ice40 and xilinx brams_init make rulesClifford Wolf2015-08-162-5/+5
* Fixed Makefile rules for generated share filesClifford Wolf2015-08-161-1/+7
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-121-6/+2
* Fixed trailing whitespacesClifford Wolf2015-07-023-6/+6
* Added output args to synth_ice40Clifford Wolf2015-05-261-2/+2
* Verific build fixesClifford Wolf2015-05-171-2/+2
* Improved xilinx "bram1" testClifford Wolf2015-04-091-1/+2
* Added memory_bram "make_outreg" featureClifford Wolf2015-04-091-0/+2
* Xilinx DRAMS: RAM64X1D, RAM128X1DClifford Wolf2015-04-093-13/+67
* Towards DRAM support in Xilinx flowClifford Wolf2015-04-095-0/+78
* Added support for initialized xilinx bramsClifford Wolf2015-04-0610-91/+314
* Added Xilinx test case for initialized bramsClifford Wolf2015-04-064-0/+80
* Added Xilinx bram black-box modulesClifford Wolf2015-04-063-0/+322
* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-041-5/+6
* Added "stat" to "synth" and "synth_xilinx"Clifford Wolf2015-02-151-0/+2
* Added final checks to "synth" and "synth_xilinx"Clifford Wolf2015-02-151-0/+10
* Disabled (unused) Xilinx tristate buffersClifford Wolf2015-02-041-6/+6
* no support for 6-series xilinx devicesClifford Wolf2015-02-011-1/+1
* Removed old XST-based xilinx examplesClifford Wolf2015-02-0111-208/+0
* Added Xilinx example for Basys3 boardClifford Wolf2015-02-019-1/+84
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 16:12:26 +0000