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* Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_req...Eddie Hung2020-01-085-1676/+518
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| * Fix abc9_xc7.box commentsEddie Hung2020-01-071-7/+14
| * Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2020-01-066-152/+642
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| | * Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-065-1674/+509
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| | * | Fix spacingEddie Hung2020-01-021-1/+1
| * | | Fix DSP48E1 simEddie Hung2020-01-061-3/+3
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| * | Wrap arrival functions inside `YOSYS tooEddie Hung2020-01-061-0/+2
| * | Fix return value of arrival time functions, fix wordEddie Hung2020-01-061-18/+14
| * | Drive $[ABCD] explicitlyEddie Hung2020-01-021-15/+21
| * | Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactorEddie Hung2020-01-022-9/+9
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| * | | ifndef __ICARUS__ -> ifdef YOSYSEddie Hung2020-01-011-2/+2
| * | | Rework abc9's DSP48E1 modelEddie Hung2020-01-015-1656/+506
* | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_r...Eddie Hung2020-01-066-498/+1003
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| * | | synth_xilinx -dff to work with abc tooEddie Hung2020-01-021-6/+14
| * | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-022-24/+44
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| | * | Merge pull request #1601 from YosysHQ/eddie/synth_retimeEddie Hung2020-01-021-3/+3
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| | | * | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
| | | * | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-2/+2
| | * | | ifdef __ICARUS__ -> ifndef YOSYSEddie Hung2020-01-011-6/+6
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| | * | Update timings for Xilinx S7 cellsEddie Hung2019-12-301-15/+35
| * | | Update commentsEddie Hung2020-01-021-11/+6
| * | | abc9 -keepff -> -dff; refactor dff operationsEddie Hung2020-01-022-58/+58
| * | | Clamp -46ps for FDPE* tooEddie Hung2020-01-011-2/+2
| * | | Restore abc9 -keepffEddie Hung2020-01-012-86/+6
| * | | Re-arrange FD orderEddie Hung2019-12-313-182/+182
| * | | Cleanup xilinx boxesEddie Hung2019-12-312-391/+425
| * | | Update abc9_xc7.box commentsEddie Hung2019-12-311-18/+18
| * | | FDCE ports to be alphabeticalEddie Hung2019-12-311-3/+3
| * | | Fix attributes on $__ABC9_ASYNC[01] whiteboxEddie Hung2019-12-311-2/+2
| * | | Fix incorrect $__ABC9_ASYNC[01] boxEddie Hung2019-12-311-2/+2
| * | | Do not offset FD* box timings due to -46ps TsuEddie Hung2019-12-301-12/+21
| * | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-308-21/+374
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| | * | Merge remote-tracking branch 'origin/master' into iopad_defaultMiodrag Milanovic2019-12-288-10/+368
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| | * | Addressed review commentsMiodrag Milanovic2019-12-211-2/+3
| | * | iopad no op for compatibility with old scriptsMiodrag Milanovic2019-12-211-0/+3
| | * | Make iopad option default for all xilinx flowsMiodrag Milanovic2019-12-211-14/+5
| * | | Tidy up abc9_map.vEddie Hung2019-12-301-103/+103
| * | | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-302-2/+98
| * | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-204-172/+240
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| * | | | Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-191-0/+78
| * | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-195-36/+55
| * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1912-77/+967
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| * | | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
| * | | | | Fix commentEddie Hung2019-12-091-1/+1
| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-065-633/+868
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| * | | | | | Remove creation of $abc9_control_wireEddie Hung2019-12-061-16/+6
| * | | | | | abc9 to use mergeability class to differentiate sync/asyncEddie Hung2019-12-061-12/+15
| * | | | | | Remove clkpartEddie Hung2019-12-051-4/+0
| * | | | | | Revert "Special abc9_clock wire to contain only clock signal"Eddie Hung2019-12-051-10/+12