diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 11:39:08 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 11:39:08 -0800 |
| commit | 27c150bfcc222512a0f3816e72ee20285acad9b4 (patch) | |
| tree | dc7139f891ad4fa854bb1fc32c3e847af73f08d0 /techlibs/xilinx | |
| parent | 7738d608e3f88695248dd49f923492e643b428dd (diff) | |
| download | yosys-27c150bfcc222512a0f3816e72ee20285acad9b4.tar.gz yosys-27c150bfcc222512a0f3816e72ee20285acad9b4.tar.bz2 yosys-27c150bfcc222512a0f3816e72ee20285acad9b4.zip | |
Fix return value of arrival time functions, fix word
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 32 |
1 files changed, 14 insertions, 18 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 7bfc36aa3..5e4529fd6 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2161,13 +2161,13 @@ module DSP48E1 ( output reg MULTSIGNOUT, output OVERFLOW, `ifdef YOSYS - (* abc9_arrival = \DSP48E1.P_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *) + (* abc9_arrival = \DSP48E1.P_arrival () *) `endif output reg signed [47:0] P, output reg PATTERNBDETECT, output reg PATTERNDETECT, `ifdef YOSYS - (* abc9_arrival = \DSP48E1.PCOUT_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *) + (* abc9_arrival = \DSP48E1.PCOUT_arrival () *) `endif output [47:0] PCOUT, output UNDERFLOW, @@ -2241,26 +2241,24 @@ module DSP48E1 ( parameter [4:0] IS_INMODE_INVERTED = 5'b0; parameter [6:0] IS_OPMODE_INVERTED = 7'b0; - function \DSP48E1.P_arrival ; - input USE_MULT, USE_DPORT; - input AREG, ADREG, BREG, CREG, DREG, MREG, PREG; + function integer \DSP48E1.P_arrival ; begin \DSP48E1.P_arrival = 0; if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin if (PREG != 0) \DSP48E1.P_arrival = 329; - // Worse-case from CREG and MREG + // Worst-case from CREG and MREG else if (CREG != 0) \DSP48E1.P_arrival = 1687; else if (MREG != 0) \DSP48E1.P_arrival = 1671; - // Worse-case from AREG and BREG + // Worst-case from AREG and BREG else if (AREG != 0) \DSP48E1.P_arrival = 2952; else if (BREG != 0) \DSP48E1.P_arrival = 2813; end else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin if (PREG != 0) \DSP48E1.P_arrival = 329; - // Worse-case from CREG and MREG + // Worst-case from CREG and MREG else if (CREG != 0) \DSP48E1.P_arrival = 1687; else if (MREG != 0) \DSP48E1.P_arrival = 1671; - // Worse-case from AREG, ADREG, BREG, DREG + // Worst-case from AREG, ADREG, BREG, DREG else if (AREG != 0) \DSP48E1.P_arrival = 3935; else if (DREG != 0) \DSP48E1.P_arrival = 3908; else if (ADREG != 0) \DSP48E1.P_arrival = 2958; @@ -2268,7 +2266,7 @@ module DSP48E1 ( end else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin if (PREG != 0) \DSP48E1.P_arrival = 329; - // Worse-case from AREG, BREG, CREG + // Worst-case from AREG, BREG, CREG else if (CREG != 0) \DSP48E1.P_arrival = 1687; else if (AREG != 0) \DSP48E1.P_arrival = 1632; else if (BREG != 0) \DSP48E1.P_arrival = 1616; @@ -2277,26 +2275,24 @@ module DSP48E1 ( // $error("Invalid DSP48E1 configuration"); end endfunction - function \DSP48E1.PCOUT_arrival ; - input USE_MULT, USE_DPORT; - input AREG, ADREG, BREG, CREG, DREG, MREG, PREG; + function integer \DSP48E1.PCOUT_arrival ; begin \DSP48E1.PCOUT_arrival = 0; if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin if (PREG != 0) \DSP48E1.PCOUT_arrival = 435; - // Worse-case from CREG and MREG + // Worst-case from CREG and MREG else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835; else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819; - // Worse-case from AREG and BREG + // Worst-case from AREG and BREG else if (AREG != 0) \DSP48E1.PCOUT_arrival = 3098; else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960; end else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin if (PREG != 0) \DSP48E1.PCOUT_arrival = 435; - // Worse-case from CREG and MREG + // Worst-case from CREG and MREG else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835; else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819; - // Worse-case from AREG, ADREG, BREG, DREG + // Worst-case from AREG, ADREG, BREG, DREG else if (AREG != 0) \DSP48E1.PCOUT_arrival = 4083; else if (DREG != 0) \DSP48E1.PCOUT_arrival = 4056; else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960; @@ -2304,7 +2300,7 @@ module DSP48E1 ( end else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin if (PREG != 0) \DSP48E1.PCOUT_arrival = 435; - // Worse-case from AREG, BREG, CREG + // Worst-case from AREG, BREG, CREG else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835; else if (AREG != 0) \DSP48E1.PCOUT_arrival = 1780; else if (BREG != 0) \DSP48E1.PCOUT_arrival = 1765; |