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* Add warning if synth_xilinx -abc9 with family != xc7Eddie Hung2019-06-271-0/+2
* Merge origin/masterEddie Hung2019-06-272-8/+9
* Update comment on boxesEddie Hung2019-06-261-2/+3
* Add "WE" to dist RAM's abc_scc_breakEddie Hung2019-06-261-3/+3
* Remove unused varEddie Hung2019-06-261-1/+1
* Add _nowide variants of LUT libraries in -nowidelut flowsEddie Hung2019-06-262-12/+28
* Merge branch 'koriakin/xc7nocarrymux' into xaigEddie Hung2019-06-261-2/+20
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| * Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriak...Eddie Hung2019-06-261-4/+24
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| | * synth_xilinx: Add -nocarry and -nomux options.Marcin Kościelnicki2019-04-301-7/+26
* | | Realistic delays for RAM32X1D tooEddie Hung2019-06-251-2/+2
* | | Add RAM32X1D box infoEddie Hung2019-06-252-4/+12
* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-255-8/+72
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| * | Add RAM32X1D supportEddie Hung2019-06-245-20/+73
* | | Use LUT delays for dist RAM delaysEddie Hung2019-06-241-4/+4
* | | Add Xilinx dist RAM as comb boxesEddie Hung2019-06-242-0/+16
* | | Add comment to xc7 boxEddie Hung2019-06-221-0/+3
* | | Carry in/out box ordering now move to end, not swap with endEddie Hung2019-06-221-12/+12
* | | Remove DFF and RAMD box info for nowEddie Hung2019-06-212-36/+0
* | | Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abcEddie Hung2019-06-201-0/+1
* | | Really permute Xilinx LUT mappings as default LUT6.I5:A6Eddie Hung2019-06-181-16/+16
* | | Revert "Fix (do not) permute LUT inputs, but permute mux selects"Eddie Hung2019-06-181-33/+31
* | | Fix (do not) permute LUT inputs, but permute mux selectsEddie Hung2019-06-181-31/+33
* | | Fix copy-pasta issueEddie Hung2019-06-171-9/+8
* | | Permute INIT for +/xilinx/lut_map.vEddie Hung2019-06-171-32/+58
* | | Simplify commentEddie Hung2019-06-171-1/+1
* | | Update LUT7/8 delays to take account for [ABC]OUTMUX delayEddie Hung2019-06-171-5/+5
* | | Try -W 300Eddie Hung2019-06-171-1/+2
* | | Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> OEddie Hung2019-06-151-2/+2
* | | As per @daveshah1 remove async DFF timing from xilinxEddie Hung2019-06-141-2/+2
* | | Add XC7_WIRE_DELAY macro to synth_xilinx.ccEddie Hung2019-06-141-1/+3
* | | Update delays based on SymbiFlow/prjxray-dbEddie Hung2019-06-141-12/+13
* | | Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}Eddie Hung2019-06-144-3/+3
* | | Remove WIP ABC9 flop supportEddie Hung2019-06-142-18/+18
* | | Make doc consistentEddie Hung2019-06-141-1/+1
* | | Fix name clashEddie Hung2019-06-131-4/+8
* | | Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-06-121-0/+8
* | | Reduce diff with masterEddie Hung2019-06-121-1/+1
* | | Fix spacingEddie Hung2019-06-121-6/+6
* | | Remove wide mux inferenceEddie Hung2019-06-124-194/+3
* | | Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-1/+1
* | | Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-1/+1
* | | Add "-W' wire delay arg to abc9, use from synth_xilinxEddie Hung2019-06-111-1/+1
* | | Disable dist RAM boxes due to comb loopEddie Hung2019-06-111-2/+2
* | | Remove #ifndef ABCEddie Hung2019-06-111-4/+0
* | | Revert "Revert "Move ff_map back after ABC for shregmap""Eddie Hung2019-06-101-5/+5
* | | Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"Eddie Hung2019-06-101-2/+2
* | | Comment out muxpack (currently broken)Eddie Hung2019-06-071-2/+2
* | | $__XILINX_MUX_ -> $__XILINX_SHIFTXEddie Hung2019-06-062-11/+11
* | | Fix muxcover and its techmappingEddie Hung2019-06-062-3/+3
* | | Run muxpack and muxcover in synth_xilinxEddie Hung2019-06-062-1/+18
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