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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 21:54:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 21:54:01 -0700 |
| commit | 152e682bd5e448aaca20e7c9349c88bbd4a8ed3b (patch) | |
| tree | ce45f1bbc121e3c5e8c1cccf3296d8bced6298a8 /techlibs/xilinx | |
| parent | 49a762ba4633ef7cda3e12f755cd5c8e97b7bf13 (diff) | |
| download | yosys-152e682bd5e448aaca20e7c9349c88bbd4a8ed3b.tar.gz yosys-152e682bd5e448aaca20e7c9349c88bbd4a8ed3b.tar.bz2 yosys-152e682bd5e448aaca20e7c9349c88bbd4a8ed3b.zip | |
Add Xilinx dist RAM as comb boxes
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/abc_xc7.box | 14 | ||||
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
2 files changed, 16 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index b5817a6e0..40b92da0c 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -29,3 +29,17 @@ CARRY4 3 1 10 8 494 465 445 - - 433 469 - - 157 592 540 520 356 - 512 548 292 - 228 580 526 507 398 385 508 528 378 380 114 + +# SLICEM/A6LUT +# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE +# Outputs: DPO SPO +RAM64X1D 4 0 15 2 +- - - - - - - 124 124 124 124 124 124 - - +124 124 124 124 124 124 - - - - - - 124 - - + +# SLICEM/A6LUT + F7[AB]MUX +# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE +# Outputs: DPO SPO +RAM128X1D 5 0 17 2 +- - - - - - - - 314 314 314 314 314 314 292 - - +347 347 347 347 347 347 296 - - - - - - - - - - diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 84939818e..8261286af 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -281,6 +281,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule +(* abc_box_id = 4, abc_scc_break="D" *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -298,6 +299,7 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule +(* abc_box_id = 5, abc_scc_break="D" *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, |