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xilinx
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Author
Age
Files
Lines
*
xilinx: Add keep attribute where appropriate
David Shah
2019-03-22
2
-25
/
+31
*
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
Clifford Wolf
2019-03-19
1
-2
/
+4
*
Merge pull request #842 from litghost/merge_upstream
Clifford Wolf
2019-03-05
10
-176
/
+570
|
\
|
*
Revert BRAM WRITE_MODE changes.
Keith Rothman
2019-03-04
1
-12
/
+12
|
*
Revert FF models to include IS_x_INVERTED parameters.
Keith Rothman
2019-03-01
1
-6
/
+34
|
*
Use singular for disabling of DRAM or BRAM inference.
Keith Rothman
2019-03-01
1
-13
/
+13
|
*
Modify arguments to match existing style.
Keith Rothman
2019-03-01
1
-6
/
+6
|
*
Changes required for VPR place and route synth_xilinx.
Keith Rothman
2019-03-01
11
-221
/
+587
*
|
Use "write_edif -pvector bra" for Xilinx EDIF files
Clifford Wolf
2019-03-05
1
-1
/
+1
|
/
*
Fix typographical and grammatical errors and inconsistencies.
whitequark
2019-01-02
1
-1
/
+1
*
Add support for Xilinx PS7 block
Eddie Hung
2018-11-10
2
-0
/
+624
*
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
Tim 'mithro' Ansell
2018-10-08
1
-3
/
+2
*
Add inout ports to cells_xtra.v
Clifford Wolf
2018-10-04
2
-2
/
+14
*
xilinx: Adding missing inout IO port to IOBUF
Tim Ansell
2018-10-03
1
-0
/
+1
*
Consistent use of 'override' for virtual methods in derived classes.
Henner Zeller
2018-07-20
1
-2
/
+2
*
Improving vpr output support.
Tim 'mithro' Ansell
2018-04-18
2
-3
/
+36
*
Squelch trailing whitespace, including meta-whitespace
Larry Doolittle
2018-03-11
1
-8
/
+8
*
Add Xilinx RAM64X1D and RAM128X1D simulation models
Clifford Wolf
2018-03-07
4
-23
/
+30
*
Add techlibs/xilinx/lut2lut.v
Clifford Wolf
2017-07-10
2
-0
/
+66
*
Added "yosys -D" feature
Clifford Wolf
2016-04-21
1
-1
/
+1
*
Added black box modules for all the 7-series design elements (as listed in ug...
Clifford Wolf
2016-03-19
4
-0
/
+3441
*
Run dffsr2dff in synth_xilinx
Clifford Wolf
2016-02-13
1
-0
/
+2
*
Added "abc -luts" option, Improved Xilinx logic mapping
Clifford Wolf
2016-02-01
1
-2
/
+2
*
Bugfix in Xilinx LUT mapping
Clifford Wolf
2015-10-30
1
-1
/
+1
*
Added examples/ top-level directory
Clifford Wolf
2015-10-13
7
-77
/
+0
*
Added read-enable to memory model
Clifford Wolf
2015-09-25
3
-19
/
+23
*
Switched to Python 3
Clifford Wolf
2015-08-22
2
-5
/
+2
*
Another bugfix for ice40 and xilinx brams_init make rules
Clifford Wolf
2015-08-16
2
-5
/
+5
*
Fixed Makefile rules for generated share files
Clifford Wolf
2015-08-16
1
-1
/
+7
*
Adjust makefiles to work with out-of-tree builds
Clifford Wolf
2015-08-12
1
-6
/
+2
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
3
-6
/
+6
*
Added output args to synth_ice40
Clifford Wolf
2015-05-26
1
-2
/
+2
*
Verific build fixes
Clifford Wolf
2015-05-17
1
-2
/
+2
*
Improved xilinx "bram1" test
Clifford Wolf
2015-04-09
1
-1
/
+2
*
Added memory_bram "make_outreg" feature
Clifford Wolf
2015-04-09
1
-0
/
+2
*
Xilinx DRAMS: RAM64X1D, RAM128X1D
Clifford Wolf
2015-04-09
3
-13
/
+67
*
Towards DRAM support in Xilinx flow
Clifford Wolf
2015-04-09
5
-0
/
+78
*
Added support for initialized xilinx brams
Clifford Wolf
2015-04-06
10
-91
/
+314
*
Added Xilinx test case for initialized brams
Clifford Wolf
2015-04-06
4
-0
/
+80
*
Added Xilinx bram black-box modules
Clifford Wolf
2015-04-06
3
-0
/
+322
*
Added "dffinit", Support for initialized Xilinx DFF
Clifford Wolf
2015-04-04
1
-5
/
+6
*
Added "stat" to "synth" and "synth_xilinx"
Clifford Wolf
2015-02-15
1
-0
/
+2
*
Added final checks to "synth" and "synth_xilinx"
Clifford Wolf
2015-02-15
1
-0
/
+10
*
Disabled (unused) Xilinx tristate buffers
Clifford Wolf
2015-02-04
1
-6
/
+6
*
no support for 6-series xilinx devices
Clifford Wolf
2015-02-01
1
-1
/
+1
*
Removed old XST-based xilinx examples
Clifford Wolf
2015-02-01
11
-208
/
+0
*
Added Xilinx example for Basys3 board
Clifford Wolf
2015-02-01
9
-1
/
+84
*
Added missing ports and parameters to xilinx brams
Clifford Wolf
2015-02-01
1
-4
/
+18
*
Fixed xilinx FDSE sim model
Clifford Wolf
2015-01-24
1
-2
/
+2
*
Various cleanups in xilinx techlib
Clifford Wolf
2015-01-18
7
-9
/
+110
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