| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Adjusting Vivado's BRAM min bits threshold for RAMB18E1 | Diego H | 2019-11-27 | 1 | -2/+5 |
| * | xilinx: Add support for UltraScale[+] BRAM mapping | David Shah | 2019-10-23 | 1 | -0/+105 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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