| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | D is 25 bits not 24 bits wide | Eddie Hung | 2019-09-19 | 1 | -1/+1 |
| * | Set more ports explicitly | Eddie Hung | 2019-09-12 | 1 | -1/+2 |
| * | Set USE_MULT and USE_SIMD | Eddie Hung | 2019-09-09 | 1 | -1/+3 |
| * | Remove signed from ports in +/xilinx/dsp_map.v | Eddie Hung | 2019-08-08 | 1 | -1/+1 |
| * | INMODE is 5 bits | Eddie Hung | 2019-08-08 | 1 | -1/+1 |
| * | Add params | Eddie Hung | 2019-07-18 | 1 | -0/+6 |
| * | Make all operands signed | Eddie Hung | 2019-07-17 | 1 | -1/+1 |
| * | Signedness | Eddie Hung | 2019-07-16 | 1 | -1/+1 |
| * | Revert drop down to 24x16 multipliers for all | Eddie Hung | 2019-07-16 | 1 | -3/+3 |
| * | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 1 | -3/+3 |
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| * | | Move DSP mapping back out to dsp_map.v | Eddie Hung | 2019-07-15 | 1 | -0/+40 |
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| * | Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little | Eddie Hung | 2019-07-10 | 1 | -40/+0 |
| * | xc7: Map combinational DSP48E1s | David Shah | 2019-07-08 | 1 | -0/+40 |
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index : iCE40/yosys | |
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