| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | xilinx: Mark IOBUFDS.IOB as external pad | Marcin Kościelnicki | 2020-03-20 | 1 | -1/+1 |
| | | |||||
| * | Remove RAMB{18,36}E1 from cells_xtra.py | Eddie Hung | 2020-02-27 | 1 | -2/+2 |
| | | |||||
| * | Get rid of (* abc9_{arrival,required} *) entirely | Eddie Hung | 2020-02-27 | 1 | -72/+4 |
| | | |||||
| * | xilinx: mark IOBUFDSE3 IOB pin as external | Piotr Binkowski | 2020-02-27 | 1 | -1/+1 |
| | | |||||
| * | Merge pull request #1661 from YosysHQ/eddie/abc9_required | Eddie Hung | 2020-02-05 | 1 | -0/+40 |
| |\ | | | | | abc9: add support for required times | ||||
| | * | Update some abc9_arrival times, add abc9_required times | Eddie Hung | 2019-12-27 | 1 | -0/+40 |
| | | | |||||
| * | | xilinx: Add simulation model for DSP48 (Virtex 4). | Marcin Kościelnicki | 2020-01-29 | 1 | -1/+1 |
| |/ | |||||
| * | xilinx: Add simulation models for remaining CLB primitives. | Marcin Kościelnicki | 2019-12-19 | 1 | -13/+13 |
| | | |||||
| * | xilinx: Add xilinx_dffopt pass (#1557) | Marcin Kościelnicki | 2019-12-18 | 1 | -1/+1 |
| | | |||||
| * | xilinx: Add models for LUTRAM cells. (#1537) | Marcin Kościelnicki | 2019-12-04 | 1 | -34/+34 |
| | | |||||
| * | xilinx: Add missing blackbox cell for BUFPLL. | Marcin Kościelnicki | 2019-11-29 | 1 | -0/+1 |
| | | |||||
| * | xilinx: Add simulation models for IOBUF and OBUFT. | Marcin Kościelnicki | 2019-11-26 | 1 | -2/+2 |
| | | |||||
| * | xilinx: Add simulation models for MULT18X18* and DSP48A*. | Marcin Kościelnicki | 2019-11-19 | 1 | -5/+5 |
| | | | | | | | | | | This adds simulation models for the following primitives: - MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3) - MULT18X18SIO (Spartan 3E, Spartan 3A) - DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1 - DSP48A1 (Spartan 6) | ||||
| * | synth_xilinx: Merge blackbox primitive libraries. | Marcin Kościelnicki | 2019-11-06 | 1 | -488/+477 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | First, there are no longer separate cell libraries for xc6s/xc7/xcu. Manually instantiating a primitive for a "wrong" family will result in yosys passing it straight through to the output, and it will be either upgraded or rejected by the P&R tool. Second, the blackbox library is expanded to cover many more families: everything from Spartan 3 up is included. Primitives for Virtex and Virtex 2 are listed in the Python file as well if we ever want to include them, but that would require having two different ISE versions (10.1 and 14.7) available when running cells_xtra.py, and so is probably more trouble than it's worth. Third, the blockram blackboxes are no longer in separate files — there is no practical reason to do so (from synthesis PoV, they are no different from any other cells_xtra blackbox), and they needlessly complicated the flow (among other things, merging them allows the user to use eg. Series 7 primitives and have them auto-upgraded to Ultrascale). Last, since xc5v logic synthesis appears to work reasonably well (the only major problem is lack of blockram inference support), xc5v is now an accepted setting for the -family option. | ||||
| * | xilinx: Add support for UltraScale[+] BRAM mapping | David Shah | 2019-10-23 | 1 | -8/+14 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | xilinx: Add simulation model for IBUFG. | Marcin Kościelnicki | 2019-10-10 | 1 | -3/+3 |
| | | |||||
| * | Remove DSP48E1 from *_cells_xtra.v | Eddie Hung | 2019-10-04 | 1 | -2/+2 |
| | | |||||
| * | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} | Eddie Hung | 2019-09-30 | 1 | -2/+2 |
| | | |||||
| * | Use extractinv for synth_xilinx -ise | Marcin Kościelnicki | 2019-09-19 | 1 | -3/+20 |
| | | |||||
| * | xilinx: Make blackbox library family-dependent. | Marcin Kościelnicki | 2019-09-15 | 1 | -45/+479 |
| | | | | | Fixes #1246. | ||||
| * | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 1 | -0/+257 |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |