aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx/cells_xtra.py
Commit message (Expand)AuthorAgeFilesLines
* xilinx: Mark IOBUFDS.IOB as external padMarcin Kościelnicki2020-03-201-1/+1
* Remove RAMB{18,36}E1 from cells_xtra.pyEddie Hung2020-02-271-2/+2
* Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-271-72/+4
* xilinx: mark IOBUFDSE3 IOB pin as externalPiotr Binkowski2020-02-271-1/+1
* Merge pull request #1661 from YosysHQ/eddie/abc9_requiredEddie Hung2020-02-051-0/+40
|\
| * Update some abc9_arrival times, add abc9_required timesEddie Hung2019-12-271-0/+40
* | xilinx: Add simulation model for DSP48 (Virtex 4).Marcin Kościelnicki2020-01-291-1/+1
|/
* xilinx: Add simulation models for remaining CLB primitives.Marcin Kościelnicki2019-12-191-13/+13
* xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-181-1/+1
* xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-041-34/+34
* xilinx: Add missing blackbox cell for BUFPLL.Marcin Kościelnicki2019-11-291-0/+1
* xilinx: Add simulation models for IOBUF and OBUFT.Marcin Kościelnicki2019-11-261-2/+2
* xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-191-5/+5
* synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-061-488/+477
* xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-231-8/+14
* xilinx: Add simulation model for IBUFG.Marcin Kościelnicki2019-10-101-3/+3
* Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-041-2/+2
* Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-301-2/+2
* Use extractinv for synth_xilinx -iseMarcin Kościelnicki2019-09-191-3/+20
* xilinx: Make blackbox library family-dependent.Marcin Kościelnicki2019-09-151-45/+479
* move attributes to wiresMarcin Kościelnicki2019-08-131-0/+257