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| author | Marcin Kościelnicki <mwk@0x04.net> | 2019-12-18 13:42:26 +0100 |
|---|---|---|
| committer | Marcin Kościelnicki <mwk@0x04.net> | 2019-12-18 13:43:43 +0100 |
| commit | a2352504031ee69efd0aac214fc947737303eb5e (patch) | |
| tree | ad93a4161ffce499d4623f0bf8dfeda44d86f734 /techlibs/xilinx/cells_xtra.py | |
| parent | aff6ad1ce09264fb7fbf43a7456a746a586bea90 (diff) | |
| download | yosys-a2352504031ee69efd0aac214fc947737303eb5e.tar.gz yosys-a2352504031ee69efd0aac214fc947737303eb5e.tar.bz2 yosys-a2352504031ee69efd0aac214fc947737303eb5e.zip | |
xilinx: Add xilinx_dffopt pass (#1557)
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index e4c580b9d..6d5adf1aa 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -66,7 +66,7 @@ CELLS = [ # CLB -- registers/latches. # Virtex 1/2/4/5, Spartan 3. Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}), - Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}), + # Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}), Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}), # Virtex 6, Spartan 6, Series 7, Ultrascale. # Cell('FDCE'), |