| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32 | Eddie Hung | 2019-02-28 | 1 | -0/+71 |
| * | Improving vpr output support. | Tim 'mithro' Ansell | 2018-04-18 | 1 | -0/+2 |
| * | Various cleanups in xilinx techlib | Clifford Wolf | 2015-01-18 | 1 | -0/+84 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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