| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Improving vpr output support. | Tim 'mithro' Ansell | 2018-04-18 | 1 | -0/+2 |
| | | | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`. | ||||
| * | Various cleanups in xilinx techlib | Clifford Wolf | 2015-01-18 | 1 | -0/+84 |
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index : iCE40/yosys | |
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