| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added read-enable to memory model | Clifford Wolf | 2015-09-25 | 1 | -7/+7 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -1/+1 |
| * | Added support for initialized xilinx brams | Clifford Wolf | 2015-04-06 | 1 | -0/+4 |
| * | Various cleanups in xilinx techlib | Clifford Wolf | 2015-01-18 | 1 | -0/+34 |
| * | Refactoring of memory_bram and xilinx brams | Clifford Wolf | 2015-01-18 | 1 | -91/+25 |
| * | Xilinx RAMB36/RAMB18 memory_bram support complete | Clifford Wolf | 2015-01-06 | 1 | -15/+27 |
| * | Towards Xilinx bram support | Clifford Wolf | 2015-01-06 | 1 | -12/+14 |
| * | Towards Xilinx bram support | Clifford Wolf | 2015-01-06 | 1 | -24/+21 |
| * | Towards Xilinx bram support | Clifford Wolf | 2015-01-05 | 1 | -1/+1 |
| * | Towards Xilinx bram support | Clifford Wolf | 2015-01-04 | 1 | -12/+114 |
| * | Progress in memory_bram | Clifford Wolf | 2014-12-31 | 1 | -3/+3 |
| * | Added memory_bram (not functional yet) | Clifford Wolf | 2014-12-31 | 1 | -0/+20 |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |