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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-04 14:23:30 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-04 14:23:30 +0100 |
| commit | 8898897f7b397a09c94e4850ef6146ee5b09677b (patch) | |
| tree | d7d641bd87a1baef0ba3584642f61b951009d263 /techlibs/xilinx/brams.txt | |
| parent | daae35319be6c8f8905f25826a8f5960cdfeda20 (diff) | |
| download | yosys-8898897f7b397a09c94e4850ef6146ee5b09677b.tar.gz yosys-8898897f7b397a09c94e4850ef6146ee5b09677b.tar.bz2 yosys-8898897f7b397a09c94e4850ef6146ee5b09677b.zip | |
Towards Xilinx bram support
Diffstat (limited to 'techlibs/xilinx/brams.txt')
| -rw-r--r-- | techlibs/xilinx/brams.txt | 126 |
1 files changed, 114 insertions, 12 deletions
diff --git a/techlibs/xilinx/brams.txt b/techlibs/xilinx/brams.txt index e5652eabf..7c5fe081f 100644 --- a/techlibs/xilinx/brams.txt +++ b/techlibs/xilinx/brams.txt @@ -1,20 +1,122 @@ -# This is a very simplified description of the capabilities of -# the Xilinx RAMB36 core. But it is a start.. -# -bram XILINX_RAMB36_SDP32 - init 1 +bram $__XILINX_RAMB36_SDP72 + abits 9 + dbits 72 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 8 + transp 2 0 + clocks 2 3 + clkpol 2 3 +endbram + +bram $__XILINX_RAMB36_SDP36 abits 10 - dbits 32 + dbits 36 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 4 + transp 2 0 + clocks 2 3 + clkpol 2 3 +endbram + +bram $__XILINX_RAMB36_SDP18 + abits 11 + dbits 18 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 2 + transp 2 0 + clocks 2 3 + clkpol 2 3 +endbram + +bram $__XILINX_RAMB36_SDP9 + abits 12 + dbits 9 groups 2 ports 1 1 - wrmode 1 0 - enable 4 0 - transp 0 2 - clocks 1 2 + wrmode 0 1 + enable 0 1 + transp 2 0 + clocks 2 3 + clkpol 2 3 endbram -match XILINX_RAMB36_SDP32 - min bits 1024 +bram $__XILINX_RAMB36_SDP4 + abits 13 + dbits 4 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 2 0 + clocks 2 3 + clkpol 2 3 +endbram + +bram $__XILINX_RAMB36_SDP2 + abits 14 + dbits 2 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 2 0 + clocks 2 3 + clkpol 2 3 +endbram + +bram $__XILINX_RAMB36_SDP1 + abits 15 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 2 0 + clocks 2 3 + clkpol 2 3 +endbram + +match $__XILINX_RAMB36_SDP72 + shuffle_enable 8 + min efficiency 20 + # or_next_if_better endmatch +# match $__XILINX_RAMB36_SDP36 +# shuffle_enable 4 +# min efficiency 20 +# or_next_if_better +# endmatch +# +# match $__XILINX_RAMB36_SDP18 +# shuffle_enable 2 +# min efficiency 20 +# or_next_if_better +# endmatch +# +# match $__XILINX_RAMB36_SDP9 +# min efficiency 20 +# or_next_if_better +# endmatch +# +# match $__XILINX_RAMB36_SDP4 +# min efficiency 20 +# or_next_if_better +# endmatch +# +# match $__XILINX_RAMB36_SDP2 +# min efficiency 20 +# or_next_if_better +# endmatch +# +# match $__XILINX_RAMB36_SDP1 +# min efficiency 20 +# endmatch + |