| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Missing endmodule | Eddie Hung | 2019-09-29 | 1 | -0/+1 |
| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 1 | -0/+162 |
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| | * | Oops. Actually use __NAME__ in ABC_DSP48E1 macro | Eddie Hung | 2019-09-25 | 1 | -1/+1 |
| | * | Grammar | Eddie Hung | 2019-09-20 | 1 | -1/+1 |
| | * | Fix DSP48E1 timing by breaking P path if MREG or PREG | Eddie Hung | 2019-09-19 | 1 | -17/+32 |
| | * | Revert "Different approach to timing" | Eddie Hung | 2019-09-19 | 1 | -63/+42 |
| | * | Different approach to timing | Eddie Hung | 2019-09-19 | 1 | -42/+63 |
| | * | Add no MULT no DPORT config | Eddie Hung | 2019-09-13 | 1 | -96/+14 |
| | * | Add support for MULT and DPORT | Eddie Hung | 2019-09-13 | 1 | -1/+89 |
| | * | Refine diagram | Eddie Hung | 2019-09-13 | 1 | -12/+14 |
| | * | Add an ASCII drawing | Eddie Hung | 2019-09-12 | 1 | -3/+22 |
| | * | Finish explanation | Eddie Hung | 2019-09-12 | 1 | -4/+10 |
| | * | Initial DSP48E1 box support | Eddie Hung | 2019-09-12 | 1 | -0/+108 |
| * | | Big rework; flop info now mostly in cells_sim.v | Eddie Hung | 2019-09-28 | 1 | -89/+1 |
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-27 | 1 | -59/+2 |
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| | * | xilinx to use abc_map.v with -max_iter 1 | Eddie Hung | 2019-08-20 | 1 | -58/+2 |
| * | | Revert "Remove sequential extension" | Eddie Hung | 2019-08-20 | 1 | -0/+89 |
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| * | Remove sequential extension | Eddie Hung | 2019-08-20 | 1 | -89/+0 |
| * | Wrap SRL{16,32} too | Eddie Hung | 2019-08-20 | 1 | -6/+26 |
| * | Wrap LUTRAMs in order to capture comb/seq behaviour | Eddie Hung | 2019-08-20 | 1 | -0/+44 |
| * | Remove mapping rules | Eddie Hung | 2019-08-20 | 1 | -33/+0 |
| * | Use abc_{map,unmap,model}.v | Eddie Hung | 2019-08-20 | 1 | -0/+148 |
 |
index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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