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path: root/techlibs/xilinx/abc_map.v
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* Remove need for $currQ port connectionEddie Hung2019-09-301-31/+38
* Add explanation to abc_map.vEddie Hung2019-09-301-0/+16
* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-291-17/+341
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| * Add techmap_autopurge to outputs in abc_map.v tooEddie Hung2019-09-231-11/+11
| * Tidy up, fix undrivenEddie Hung2019-09-191-32/+34
| * $__ABC_REG to have WIDTH parameterEddie Hung2019-09-191-16/+16
| * Fix DSP48E1 timing by breaking P path if MREG or PREGEddie Hung2019-09-191-30/+27
| * Revert "Different approach to timing"Eddie Hung2019-09-191-80/+61
| * Different approach to timingEddie Hung2019-09-191-61/+80
| * Suppress $anyseq warningsEddie Hung2019-09-191-15/+32
| * Use (* techmap_autopurge *) to suppress techmap warningsEddie Hung2019-09-191-55/+55
| * Fix copy-pasteEddie Hung2019-09-181-2/+2
| * Add `undef DSP48E1_INSTEddie Hung2019-09-131-4/+5
| * Add no MULT no DPORT configEddie Hung2019-09-131-127/+91
| * Add support for MULT and DPORTEddie Hung2019-09-131-4/+130
| * Rename to techmap_guardEddie Hung2019-09-121-2/+3
| * Initial DSP48E1 box supportEddie Hung2019-09-121-0/+216
* | Big rework; flop info now mostly in cells_sim.vEddie Hung2019-09-281-31/+46
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-271-15/+13
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| * Resolve TODO with pin assignments for SRL*Eddie Hung2019-09-041-4/+2
| * xilinx to use abc_map.v with -max_iter 1Eddie Hung2019-08-201-13/+13
* | Revert "Remove sequential extension"Eddie Hung2019-08-201-0/+97
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* Remove sequential extensionEddie Hung2019-08-201-97/+0
* LUTMUX -> LUTMUX6Eddie Hung2019-08-201-2/+2
* Remove delays from abc_map.vEddie Hung2019-08-201-5/+2
* TypoEddie Hung2019-08-201-1/+1
* Wrap SRL{16,32} tooEddie Hung2019-08-201-0/+36
* Wrap LUTRAMs in order to capture comb/seq behaviourEddie Hung2019-08-201-0/+69
* Use abc_{map,unmap,model}.vEddie Hung2019-08-201-0/+120