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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-18 12:19:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-18 12:19:16 -0700 |
| commit | 25e0f0c3765060b7ce25a0c58bc926b90dba304d (patch) | |
| tree | 3843f288eedaeaf7ac89fa1b6c8796cf06d70b59 /techlibs/xilinx/abc_map.v | |
| parent | 347cbf59bd45345663defa9c99c7fc6563404da6 (diff) | |
| download | yosys-25e0f0c3765060b7ce25a0c58bc926b90dba304d.tar.gz yosys-25e0f0c3765060b7ce25a0c58bc926b90dba304d.tar.bz2 yosys-25e0f0c3765060b7ce25a0c58bc926b90dba304d.zip | |
Fix copy-paste
Diffstat (limited to 'techlibs/xilinx/abc_map.v')
| -rw-r--r-- | techlibs/xilinx/abc_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 31fd79861..1f369fc19 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -381,7 +381,7 @@ __CELL__ #( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_INST(\$__ABC_DSP48E1_MULTD_PORT ) + `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT ) end else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin wire [29:0] iA; @@ -422,7 +422,7 @@ __CELL__ #( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_INST(\$__ABC_DSP48E1_MULTD_PORT ) + `DSP48E1_INST(\$__ABC_DSP48E1 ) end else $error("Invalid DSP48E1 configuration"); |