iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add Xilinx RAM64X1D and RAM128X1D simulation models	Clifford Wolf	2018-03-07	1	-1/+0
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*	Add techlibs/xilinx/lut2lut.v	Clifford Wolf	2017-07-10	1	-0/+1
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*	Added black box modules for all the 7-series design elements (as listed in ↵	Clifford Wolf	2016-03-19	1	-0/+1
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*	Switched to Python 3	Clifford Wolf	2015-08-22	1	-1/+1
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*	Another bugfix for ice40 and xilinx brams_init make rules	Clifford Wolf	2015-08-16	1	-1/+1
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*	Fixed Makefile rules for generated share files	Clifford Wolf	2015-08-16	1	-1/+7
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*	Adjust makefiles to work with out-of-tree builds	Clifford Wolf	2015-08-12	1	-6/+2
\| \| \| \|	This is based on work done by Larry Doolittle
*	Verific build fixes	Clifford Wolf	2015-05-17	1	-2/+2
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*	Towards DRAM support in Xilinx flow	Clifford Wolf	2015-04-09	1	-0/+3
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*	Added support for initialized xilinx brams	Clifford Wolf	2015-04-06	1	-0/+21
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*	Added Xilinx bram black-box modules	Clifford Wolf	2015-04-06	1	-0/+1
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*	Various cleanups in xilinx techlib	Clifford Wolf	2015-01-18	1	-3/+3
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*	Added MUXCY and XORCY support to synth_xilinx	Clifford Wolf	2015-01-17	1	-0/+1
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*	Added add_share_file Makefile macro	Clifford Wolf	2015-01-08	1	-13/+4
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*	Towards Xilinx bram support	Clifford Wolf	2015-01-04	1	-1/+9
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*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24	1	-2/+2
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*	Added synth_xilinx command	Clifford Wolf	2013-10-27	1	-0/+9