iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	machxo2: Use `memory_libmap` pass.	Marcelina Kościelnicka	2022-05-18	1	-0/+121
*	iopadmap: Add native support for negative-polarity output enable.	Marcelina Kościelnicka	2021-11-09	1	-2/+2
*	machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ...	William D. Jones	2021-02-23	1	-11/+5
*	machxo2: Add DCCA and DCMA blackbox primitives.	William D. Jones	2021-02-23	1	-0/+17
*	machxo2: Fix reversed interpretation of REG_SD config bits.	William D. Jones	2021-02-23	1	-2/+2
*	machxo2: Tristate is active-low.	William D. Jones	2021-02-23	1	-2/+2
*	machxo2: Fix typos in FACADE_FF sim model.	William D. Jones	2021-02-23	1	-5/+4
*	machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.	William D. Jones	2021-02-23	1	-3/+3
*	machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to...	William D. Jones	2021-02-23	1	-0/+12
*	machxo2: Add missing OSCH oscillator primitive.	William D. Jones	2021-02-23	1	-0/+10
*	machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.	William D. Jones	2021-02-23	1	-1/+1
*	machxo2: Fix cells_sim typo where OFX1 was multiply-driven.	William D. Jones	2021-02-23	1	-1/+1
*	machxo2: Add initial value for Q in FACADE_FF.	William D. Jones	2021-02-23	1	-0/+2
*	machxo2: Add FACADE_IO simulation model. More comments on models.	William D. Jones	2021-02-23	1	-0/+25
*	machxo2: Add FACADE_SLICE simulation model.	William D. Jones	2021-02-23	1	-0/+83
*	machxo2: Improve FACADE_FF simulation model.	William D. Jones	2021-02-23	1	-12/+20
*	machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.	William D. Jones	2021-02-23	1	-2/+2
*	machxo2: Fix more oversights in machxo2 models. logic.ys test passes.	William D. Jones	2021-02-23	1	-1/+1
*	machxo2: Fix typos. test/arch/run-test.sh passes.	William D. Jones	2021-02-23	1	-1/+1
*	machxo2: Create basic techlibs and synth_machxo2 pass.	William D. Jones	2021-02-23	1	-0/+62