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| author | William D. Jones <thor0505@comcast.net> | 2020-11-20 18:53:09 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | 427fed23eec2f09eb93bf08a5ac1a4cd41d0a2c2 (patch) | |
| tree | 17aef092bc13e5b10c8ba4858ed514d54742a4d4 /techlibs/machxo2/cells_sim.v | |
| parent | 19b043344c67a0ce5a8a14ef2960f366980c9873 (diff) | |
| download | yosys-427fed23eec2f09eb93bf08a5ac1a4cd41d0a2c2.tar.gz yosys-427fed23eec2f09eb93bf08a5ac1a4cd41d0a2c2.tar.bz2 yosys-427fed23eec2f09eb93bf08a5ac1a4cd41d0a2c2.zip | |
machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.
Diffstat (limited to 'techlibs/machxo2/cells_sim.v')
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index 8db73c50c..2c4d2f462 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -2,7 +2,7 @@ module LUT4 #( parameter [15:0] INIT = 0 ) ( input A, B, C, D, - output F + output Z ); wire [3:0] I; wire [3:0] I_pd; @@ -14,7 +14,7 @@ module LUT4 #( endgenerate assign I = {D, C, B, A}; - assign F = INIT[I_pd]; + assign Z = INIT[I_pd]; endmodule module FACADE_FF #( |