| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
| |
|
|
|
|
| |
Signed-off-by: gatecat <gatecat@ds0.me>
|
|
|
|
| |
Signed-off-by: gatecat <gatecat@ds0.me>
|
|
|
|
|
|
| |
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
|
|
|
|
| |
This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
|
|
|
|
| |
This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
|
| |
|
| |
|
|
|
|
|
|
|
|
|
|
| |
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
|
| |
|
| |
|
|
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
|