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* intel_alm: M10K write-enable is negative-trueLofty2022-03-091-2/+7
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* intel_alm: preliminary Arria V supportLofty2021-11-251-1/+12
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* intel_alm: Add global buffer insertiongatecat2021-05-151-0/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add IO buffer insertiongatecat2021-05-151-0/+44
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-261-3/+45
| | | | | | Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-271-1/+50
| | | | This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
* Revert "intel_alm: direct M10K instantiation"Lofty2020-07-131-45/+0
| | | | This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-051-0/+45
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* intel_alm: DSP inferenceDan Ravensloft2020-07-051-0/+23
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* intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-071-0/+39
| | | | | | | | | | By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
* intel_alm: cleanup duplicationDan Ravensloft2020-04-241-0/+63
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* synth_intel_alm: VQM supportDan Ravensloft2020-04-151-6/+2
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* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-151-0/+23
By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).