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authorgatecat <gatecat@ds0.me>2021-05-15 14:23:22 +0100
committergatecat <gatecat@ds0.me>2021-05-15 22:37:06 +0100
commit5dba138c87762d4b5bb7b9348da372a92fab1cc0 (patch)
tree764f5d928b3e06b6a4884d5d1b14e4533003d18e /techlibs/intel_alm/common/quartus_rename.v
parent3421979f00664443c77b0899d34438f979b4c51c (diff)
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intel_alm: Add IO buffer insertion
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'techlibs/intel_alm/common/quartus_rename.v')
-rw-r--r--techlibs/intel_alm/common/quartus_rename.v44
1 files changed, 44 insertions, 0 deletions
diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v
index 3b4628675..964a094dd 100644
--- a/techlibs/intel_alm/common/quartus_rename.v
+++ b/techlibs/intel_alm/common/quartus_rename.v
@@ -2,11 +2,15 @@
`define LCELL cyclonev_lcell_comb
`define MAC cyclonev_mac
`define MLAB cyclonev_mlab_cell
+`define IBUF cyclonev_io_ibuf
+`define OBUF cyclonev_io_obuf
`endif
`ifdef cyclone10gx
`define LCELL cyclone10gx_lcell_comb
`define MAC cyclone10gx_mac
`define MLAB cyclone10gx_mlab_cell
+`define IBUF cyclone10gx_io_ibuf
+`define OBUF cyclone10gx_io_obuf
`endif
module __MISTRAL_VCC(output Q);
@@ -233,3 +237,43 @@ parameter B_SIGNED = 1;
);
endmodule
+
+module MISTRAL_IB(input PAD, output O);
+`IBUF #(
+ .bus_hold("false"),
+ .differential_mode("false")
+) _TECHMAP_REPLACE_ (
+ .i(PAD),
+ .o(O)
+);
+endmodule
+
+module MISTRAL_OB(output PAD, input I, OE);
+`OBUF #(
+ .bus_hold("false"),
+ .differential_mode("false")
+) _TECHMAP_REPLACE_ (
+ .i(I),
+ .o(PAD),
+ .oe(OE)
+);
+endmodule
+
+module MISTRAL_IO(output PAD, input I, OE, output O);
+`IBUF #(
+ .bus_hold("false"),
+ .differential_mode("false")
+) ibuf (
+ .i(PAD),
+ .o(O)
+);
+
+`OBUF #(
+ .bus_hold("false"),
+ .differential_mode("false")
+) obuf (
+ .i(I),
+ .o(PAD),
+ .oe(OE)
+);
+endmodule