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* Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-041-2/+2
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
* Changes in GoWin synth commands and ALU primitive supportDiego H2018-12-031-8/+8
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-6/+6
* Add "synth_intel --noiopads"Clifford Wolf2018-04-301-2/+11
* Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal val...c60k282018-03-317-60/+178
* Add "dffinit -highlow" and fix synth_intelClifford Wolf2018-01-091-1/+1
* Initial Cyclone 10 supportdh732017-11-085-1/+308
* Clean whitespace and permissions in techlibs/intelLarry Doolittle2017-10-0521-190/+190
* Rename "write_verilog -nobasenradix" to "write_verilog -decimal"Clifford Wolf2017-10-031-4/+1
* Tested and working altsyncarm without init filesdh732017-10-012-57/+59
* Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ...dh732017-10-0121-0/+2721