| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix formatting for synth_intel.cc | Ben Widawsky | 2019-05-09 | 1 | -222/+211 |
| * | Unify usage of noflatten among architectures | Miodrag Milanovic | 2019-01-04 | 1 | -2/+2 |
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -6/+6 |
| * | Add "synth_intel --noiopads" | Clifford Wolf | 2018-04-30 | 1 | -2/+11 |
| * | Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal val... | c60k28 | 2018-03-31 | 1 | -4/+23 |
| * | Add "dffinit -highlow" and fix synth_intel | Clifford Wolf | 2018-01-09 | 1 | -1/+1 |
| * | Initial Cyclone 10 support | dh73 | 2017-11-08 | 1 | -1/+5 |
| * | Clean whitespace and permissions in techlibs/intel | Larry Doolittle | 2017-10-05 | 1 | -3/+3 |
| * | Rename "write_verilog -nobasenradix" to "write_verilog -decimal" | Clifford Wolf | 2017-10-03 | 1 | -4/+1 |
| * | Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ... | dh73 | 2017-10-01 | 1 | -0/+241 |
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index : iCE40/yosys | |
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