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techlibs
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ice40
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synth_ice40.cc
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Author
Age
Files
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*
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
Eddie Hung
2019-12-19
1
-0
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+5
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techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
Eddie Hung
2019-12-06
1
-0
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+5
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ice40_wrapcarry to really preserve attributes via -unwrap option
Eddie Hung
2019-12-09
1
-0
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+1
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Add "autoname" pass and use it in "synth_ice40"
Clifford Wolf
2019-11-13
1
-0
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+1
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Call memory_dff before DSP mapping to reserve registers (fixes #1447)
N. Engelhardt
2019-10-17
1
-0
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+1
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Rename abc_* names/attributes to more precisely be abc9_*
Eddie Hung
2019-10-04
1
-2
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+2
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Panic over. Model was elsewhere. Re-arrange for consistency
Eddie Hung
2019-10-04
1
-1
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+2
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Re-order
Eddie Hung
2019-09-27
1
-1
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+1
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select once
Eddie Hung
2019-09-26
1
-5
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+7
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Stop trying to be too smart by prematurely optimising
Eddie Hung
2019-09-26
1
-3
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+5
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Only wreduce on t:$add
Eddie Hung
2019-09-25
1
-1
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+1
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Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
Eddie Hung
2019-09-20
1
-2
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+1
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Revert "Move mul2dsp before wreduce"
Eddie Hung
2019-09-20
1
-4
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+5
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Move mul2dsp before wreduce
Eddie Hung
2019-09-20
1
-5
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+4
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Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2
Eddie Hung
2019-09-19
1
-1
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+3
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Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-09-05
1
-1
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+8
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LX -> LP
Eddie Hung
2019-08-28
1
-1
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+1
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Specify ice40 family to cells_sim.v using define
Eddie Hung
2019-08-28
1
-1
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+8
*
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Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-08-20
1
-6
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+7
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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad...
Eddie Hung
2019-08-12
1
-6
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+7
*
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Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-08-12
1
-1
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+1
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Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
David Shah
2019-08-10
1
-7
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+6
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Merge pull request #1258 from YosysHQ/eddie/cleanup
Clifford Wolf
2019-08-10
1
-1
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+1
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stoi -> atoi
Eddie Hung
2019-08-07
1
-1
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+1
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*
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Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER
Eddie Hung
2019-08-07
1
-1
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+3
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Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER
Eddie Hung
2019-08-07
1
-5
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+4
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Add wreduce to synth_ice40 -dsp as well
Eddie Hung
2019-08-09
1
-0
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+1
*
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Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
Eddie Hung
2019-08-08
1
-1
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+1
*
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Run "opt_expr -fine" instead of "wreduce" due to #1213
Eddie Hung
2019-08-07
1
-2
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+1
*
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DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH
Eddie Hung
2019-08-01
1
-1
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+1
*
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Remove debug
Eddie Hung
2019-07-22
1
-1
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+0
*
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Rename according to vendor doc TN1295
Eddie Hung
2019-07-22
1
-0
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+1
*
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opt and wreduce necessary for -dsp
Eddie Hung
2019-07-22
1
-2
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+4
*
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Indirection via $__soft_mul
Eddie Hung
2019-07-19
1
-0
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+1
*
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Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold
Eddie Hung
2019-07-19
1
-1
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+1
*
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Merge remote-tracking branch 'origin/master' into ice40dsp
Eddie Hung
2019-07-18
1
-5
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+6
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Merge pull request #1184 from whitequark/synth-better-labels
Clifford Wolf
2019-07-18
1
-2
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+2
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synth_{ice40,ecp5}: more sensible pass label naming.
whitequark
2019-07-16
1
-2
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+2
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ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
Sylvain Munaut
2019-07-16
1
-1
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+1
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*
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Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
Eddie Hung
2019-07-16
1
-2
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+3
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Map to and from this box if -abc9
Eddie Hung
2019-07-12
1
-2
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+3
*
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synth_ice40 to decompose into 16x16
Eddie Hung
2019-07-18
1
-1
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+3
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*
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synth_ice40: switch -relut to be always on.
whitequark
2019-07-11
1
-10
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+4
*
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synth_ice40: fix help text typo. NFC.
whitequark
2019-07-11
1
-1
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+1
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Error out if -abc9 and -retime specified
Eddie Hung
2019-07-10
1
-1
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+4
*
Update synth_ice40 -device doc to be relevant for -abc9 only
Eddie Hung
2019-06-28
1
-2
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+2
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Extraneous newline
Eddie Hung
2019-06-27
1
-1
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+0
*
abc9: Add wire delays to synth_ice40
David Shah
2019-06-26
1
-2
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+10
*
Resolve comments from @daveshah1
Eddie Hung
2019-06-14
1
-1
/
+1
*
Make doc consistent
Eddie Hung
2019-06-14
1
-1
/
+1
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