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author | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 08:52:14 -0700 |
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committer | GitHub <noreply@github.com> | 2019-07-16 08:52:14 -0700 |
commit | ba8ccbdea88fe432187e2481a8525cc1c53b4cf4 (patch) | |
tree | ce3c29d03229cfb18392f2ddc835ce66056aeee4 /techlibs/ice40/synth_ice40.cc | |
parent | a1a04ea79c4d006baa7204ba5ca77870f45aa633 (diff) | |
parent | 5fb27c071bb072644dbb38cf8a516628c2afe15b (diff) | |
download | yosys-ba8ccbdea88fe432187e2481a8525cc1c53b4cf4.tar.gz yosys-ba8ccbdea88fe432187e2481a8525cc1c53b4cf4.tar.bz2 yosys-ba8ccbdea88fe432187e2481a8525cc1c53b4cf4.zip |
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
-rw-r--r-- | techlibs/ice40/synth_ice40.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 0474e76e9..b3d30791a 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -238,7 +238,7 @@ struct SynthIce40Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -lib -D_ABC +/ice40/cells_sim.v"); + run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run("proc"); } @@ -294,7 +294,7 @@ struct SynthIce40Pass : public ScriptPass if (nocarry) run("techmap"); else - run("techmap -map +/techmap.v -map +/ice40/arith_map.v"); + run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : "")); if (retime || help_mode) run(abc + " -dff", "(only if -retime)"); run("ice40_opt"); @@ -338,6 +338,7 @@ struct SynthIce40Pass : public ScriptPass else wire_delay = 250; run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); + run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v"); } else run(abc + " -dress -lut 4", "(skip if -noabc)"); |