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* Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
* Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
* Revert "Optimise write_xaiger"Eddie Hung2019-12-201-5/+0
* Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-191-0/+5
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| * techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-061-0/+5
* | ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-091-0/+1
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* Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-131-0/+1
* Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-171-0/+1
* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-2/+2
* Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-041-1/+2
* Re-orderEddie Hung2019-09-271-1/+1
* select onceEddie Hung2019-09-261-5/+7
* Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-261-3/+5
* Only wreduce on t:$addEddie Hung2019-09-251-1/+1
* Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40Eddie Hung2019-09-201-2/+1
* Revert "Move mul2dsp before wreduce"Eddie Hung2019-09-201-4/+5
* Move mul2dsp before wreduceEddie Hung2019-09-201-5/+4
* Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2Eddie Hung2019-09-191-1/+3
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-051-1/+8
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| * LX -> LPEddie Hung2019-08-281-1/+1
| * Specify ice40 family to cells_sim.v using defineEddie Hung2019-08-281-1/+8
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-201-6/+7
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| * Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad...Eddie Hung2019-08-121-6/+7
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-121-1/+1
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| * Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-101-7/+6
| * Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-101-1/+1
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| | * stoi -> atoiEddie Hung2019-08-071-1/+1
| * | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-071-1/+3
| * | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDEREddie Hung2019-08-071-5/+4
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* | Add wreduce to synth_ice40 -dsp as wellEddie Hung2019-08-091-0/+1
* | Rework ice40_dsp to map to SB_MAC16 earlier, and check before packingEddie Hung2019-08-081-1/+1
* | Run "opt_expr -fine" instead of "wreduce" due to #1213Eddie Hung2019-08-071-2/+1
* | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTHEddie Hung2019-08-011-1/+1
* | Remove debugEddie Hung2019-07-221-1/+0
* | Rename according to vendor doc TN1295Eddie Hung2019-07-221-0/+1
* | opt and wreduce necessary for -dspEddie Hung2019-07-221-2/+4
* | Indirection via $__soft_mulEddie Hung2019-07-191-0/+1
* | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this thresholdEddie Hung2019-07-191-1/+1
* | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-181-5/+6
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| * Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-181-2/+2
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| | * synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-161-2/+2
| * | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port mapSylvain Munaut2019-07-161-1/+1
| * | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-161-2/+3
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| | * Map to and from this box if -abc9Eddie Hung2019-07-121-2/+3
* | | synth_ice40 to decompose into 16x16Eddie Hung2019-07-181-1/+3
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* | synth_ice40: switch -relut to be always on.whitequark2019-07-111-10/+4
* | synth_ice40: fix help text typo. NFC.whitequark2019-07-111-1/+1
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* Error out if -abc9 and -retime specifiedEddie Hung2019-07-101-1/+4
* Update synth_ice40 -device doc to be relevant for -abc9 onlyEddie Hung2019-06-281-2/+2
* Extraneous newlineEddie Hung2019-06-271-1/+0