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* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-3/+1
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* synth_ice40: Use opt_dff.Marcelina Kościelnicka2020-07-301-8/+4
| | | | | | | | | The main part is converting ice40_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the mux patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* ice40: Use dfflegalize.Marcelina Kościelnicka2020-07-051-5/+4
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* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-231-1/+1
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* Use C++11 final/override keywords.whitequark2020-06-181-5/+5
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* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-141-1/+1
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* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-1/+1
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+1
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* ice40: synth_ice40 cleanupEddie Hung2020-05-141-13/+3
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* ice40: add synth_ice40 -dff option, support with -abc9Eddie Hung2020-05-141-8/+28
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* ice40: fix whitespaceEddie Hung2020-05-121-15/+14
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* synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-041-8/+16
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* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-101-1/+3
|\ | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-1/+3
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* | Fix indentation in `techlibs/ice40/synth_ice40.cc`.Alberto Gonzalez2020-04-011-4/+4
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* | ice40: Map unmapped 'mince' DFFs to gate levelDavid Shah2020-03-201-0/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-031-4/+22
|\ \ | | | | | | Add -flowmap option to `synth{,_ice40}`
| * | Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-281-4/+22
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* | ice40: specify fixesEddie Hung2020-02-271-9/+9
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* | ice40: move over to specify blocks for -abc9Eddie Hung2020-02-271-3/+3
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* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-0/+1
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* synth_ice40: call wreduce before mul2dspEddie Hung2020-01-171-1/+2
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* synth_ice40: -abc2 to always use `abc` even if `-abc9`Eddie Hung2020-01-121-10/+10
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* Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
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* Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
| | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
* Revert "Optimise write_xaiger"Eddie Hung2019-12-201-5/+0
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* Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-191-0/+5
|\ | | | | Optimise write_xaiger
| * techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-061-0/+5
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* | ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-091-0/+1
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* Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-131-0/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-171-0/+1
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* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-2/+2
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* Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-041-1/+2
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* Re-orderEddie Hung2019-09-271-1/+1
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* select onceEddie Hung2019-09-261-5/+7
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* Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-261-3/+5
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* Only wreduce on t:$addEddie Hung2019-09-251-1/+1
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* Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40Eddie Hung2019-09-201-2/+1
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* Revert "Move mul2dsp before wreduce"Eddie Hung2019-09-201-4/+5
| | | | This reverts commit e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab.
* Move mul2dsp before wreduceEddie Hung2019-09-201-5/+4
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* Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2Eddie Hung2019-09-191-1/+3
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* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-051-1/+8
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| * LX -> LPEddie Hung2019-08-281-1/+1
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| * Specify ice40 family to cells_sim.v using defineEddie Hung2019-08-281-1/+8
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* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-201-6/+7
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| * Revert "Merge pull request #1280 from ↵Eddie Hung2019-08-121-6/+7
| | | | | | | | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-121-1/+1
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| * Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-101-7/+6
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| * Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-101-1/+1
| |\ | | | | | | Cleanup a few barnacles across codebase